Abstract: A method for manufacturing a memory includes the following operations. A substrate and a plurality of separate initial bit line contact structures are provided, in which a plurality of active regions are formed in the substrate, and each of the initial bit line contact structures is electrically connected with the active regions, and each of the initial bit line contact structures is partially located in the substrate. Pseudo-bit line structures on the tops of the initial bit line contact structures are formed. The initial bit line contact structures are etched to form bit line contact layers and gaps between the substrate and the side walls of the bit line contact layers. First dielectric layers are formed on the side walls of the pseudo-bit line structures, in which the first dielectric layers are also located right above the gaps.

Abstract: A manufacturing method of a memory includes: providing a substrate and a bit line contact layer; forming a dummy bit line structure on top of the bit line contact layer; forming a spacer layer on the sidewall of both the dummy bit line structure and the bit line contact layer; forming a dielectric layer on the sidewall of the spacer layer; forming a sacrificial layer filling the area between adjacent dummy bit line structures, wherein the sacrificial layer covers the sidewall of the dielectric layer; after the sacrificial layer is formed, removing the dummy bit line structure; forming a bit line conductive portion which fills the hole and covers the bit line contact layer; and, after the bit line conductive portion is formed, removing the spacer layer.

Abstract: A method for forming a storage node contact structure and semiconductor structure are provided. The method includes providing a substrate having a surface on which bit line structures are formed; forming a groove at a part, corresponding to an active region, of bottom of the contact hole; and growing a silicon crystal from the groove in the contact hole by using an epitaxial growth process, and controlling growth rates of the silicon crystal in a first and second directions in a growth process to enable the growth rate of the silicon crystal in the first direction to be greater than the growth rate of the silicon crystal in the second direction at beginning of growth and enable the growth rate of the silicon crystal in the first direction to be equal to the growth rate of the silicon crystal in the second direction at end of the growth.

Abstract: A method for manufacturing a memory includes: providing a substrate and multiple discrete pseudo bit line contact layers, a plurality of active areas being provided in the substrate, and each bit line contact layer being electrically connected to the active areas; forming pseudo bit line structures at tops of the pseudo bit line contact layers; forming sacrificial layers that fill regions between the adjacent pseudo bit line structures and are located on side walls of the pseudo bit line structures and the pseudo bit line contact layers; after forming the sacrificial layers, removing the pseudo bit line structures to form through holes exposing the pseudo bit line contact layers; removing the pseudo bit line contact layers to form through holes in the substrate; and forming bit line contact layers that fill the through holes in the substrate and are electrically connected to the active areas.

Abstract: The present disclosure provides a forming method of a memory and a memory. The method includes: providing a substrate, wherein the substrate includes at least word line structures and active areas, and a bottom dielectric layer and a bit line contact layer located on a top surface of the substrate, the bottom dielectric layer has bit line contact openings, the bit line contact openings expose the active areas in the substrate, and the bit line contact layer covers the bottom dielectric layer and fills the bit line contact openings; etching parts of the bit line contact layer, and forming first bit line contact layer with different heights; forming a conductive layer, a top surface of the conductive layer is located at different heights in a direction perpendicular to an extension direction of the word line structures.

Abstract: Some embodiments of the present application provide a memory forming method and a memory. The method includes: providing a substrate including at least word line structures and active regions, and bottom dielectric layers and bit line contact layers located on a top surface of the substrate, the bottom dielectric layer having bit line contact openings exposing the active regions in the substrate, and the bit line contact layers covering the bottom dielectric layers and filling the bit line contact openings; etching part of the bit line contact layers to form the bit line contact layers of different heights; forming conductive layers, top surfaces of the conductive layers being at the same height in a direction perpendicular to an extension direction of the word line structures; and the top surfaces of the conductive layers being at different heights in the extension direction of the word line structures; forming top dielectric layers.

Abstract: Provided is a method for forming a storage node contact structure and a semiconductor structure. The method for forming a storage node contact structure comprises: providing a substrate, bit line structures being formed on a surface of the substrate and contact holes being formed between the bit line structures; and growing silicon crystal in the contact holes and adding a doping source in a growth process, in which a doping concentration of the doping source when the growth is over is greater than a doping concentration when the growth is started so as to form silicon crystal gradual change structures in the contact holes, in which the silicon crystal changes from monocrystalline silicon to heavily doped polycrystalline silicon.

Abstract: A method for forming a storage node contact structure and semiconductor structure are provided. The method includes providing a substrate having a surface on which bit line structures are formed; forming a groove at a part, corresponding to an active region, of bottom of the contact hole; and growing a silicon crystal from the groove in the contact hole by using an epitaxial growth process, and controlling growth rates of the silicon crystal in a first and second directions in a growth process to enable the growth rate of the silicon crystal in the first direction to be greater than the growth rate of the silicon crystal in the second direction at beginning of growth and enable the growth rate of the silicon crystal in the first direction to be equal to the growth rate of the silicon crystal in the second direction at end of the growth.

Abstract: A method for manufacturing a memory includes the following operations. A substrate and a plurality of separate initial bit line contact structures are provided, in which a plurality of active regions are formed in the substrate, and each of the initial bit line contact structures is electrically connected with the active regions, and each of the initial bit line contact structures is partially located in the substrate. Pseudo-bit line structures on the tops of the initial bit line contact structures are formed. The initial bit line contact structures are etched to form bit line contact layers and gaps between the substrate and the side walls of the bit line contact layers. First dielectric layers are formed on the side walls of the pseudo-bit line structures, in which the first dielectric layers are also located right above the gaps.

Abstract: A method for manufacturing a memory includes: providing a substrate and multiple discrete pseudo bit line contact layers, a plurality of active areas being provided in the substrate, and each bit line contact layer being electrically connected to the active areas; forming pseudo bit line structures at tops of the pseudo bit line contact layers; forming sacrificial layers that fill regions between the adjacent pseudo bit line structures and are located on side walls of the pseudo bit line structures and the pseudo bit line contact layers; after forming the sacrificial layers, removing the pseudo bit line structures to form through holes exposing the pseudo bit line contact layers; removing the pseudo bit line contact layers to form through holes in the substrate; and forming bit line contact layers that fill the through holes in the substrate and are electrically connected to the active areas.

Abstract: A manufacturing method of a memory includes: providing a substrate and a bit line contact layer; forming a dummy bit line structure on top of the bit line contact layer; forming a spacer layer on the sidewall of both the dummy bit line structure and the bit line contact layer; forming a dielectric layer on the sidewall of the spacer layer; forming a sacrificial layer filling the area between adjacent dummy bit line structures, wherein the sacrificial layer covers the sidewall of the dielectric layer; after the sacrificial layer is formed, removing the dummy bit line structure; forming a bit line conductive portion which fills the hole and covers the bit line contact layer; and, after the bit line conductive portion is formed, removing the spacer layer.

Abstract: A method for manufacturing a memory includes the following steps. A substrate and bit line contact layers are provided. Pseudo bit line structures are formed at tops of the bit line contact layers. Sacrificial layers filling regions between adjacent bit line structures are formed, and the sacrificial layers are located on side walls of the pseudo bit line structures and side walls of the bit line contact layers. After forming the sacrificial layers, the pseudo bit line structures are removed to form through holes exposing the bit line contact layers. Bit line conductive parts filling the through holes and covering the bit line contact layers are formed.

Abstract: A method for forming a memory device includes: providing a substrate including at least word line structures and active regions, and a bottom dielectric layer and bit line contact layers that are on a top surface of the substrate; part of the bit line contact layers are etched to form bit line contact layers at different heights; conducting layers are formed, top surfaces of the conducting layers being at different heights in a direction perpendicular to an extension direction of the word line structure, and the top surfaces of the conducting layers being at different heights in the extension direction of the word line structure; top dielectric layers are formed; and etching is performed to form separate bit line structures.