Patents by Inventor Lino A. Velo

Lino A. Velo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220142488
    Abstract: Automated systems and methods are presented for determining the physiological response of human or suitable animal subjects to physical exertion. The methods and systems can include monitoring sensors that capture the motion of the subject along with corresponding physiological data, and can track such motion for the duration of a period of physical exertion. The system is able to acquire an initial stream of physiological data from the subject during a range of physical exertion activities that are representative of the events intended to be monitored with the proposed method and system, enabling a corresponding dynamic physiological response model to be created. The motion tracking system and physiological response model can then be used to predict the physiological response to physical exertion events under a prescribed framework, including applications during real-time event monitoring.
    Type: Application
    Filed: May 13, 2021
    Publication date: May 12, 2022
    Applicant: Salutron, Inc.
    Inventor: Lino Velo
  • Publication number: 20220143462
    Abstract: Automated systems and methods are presented for determining the physiological response of human or suitable animal subjects to physical exertion. The methods and systems can include monitoring sensors that capture the motion of the subject along with corresponding physiological data, and can track such motion for the duration of a period of physical exertion. The system is able to acquire an initial stream of physiological data from the subject during a range of physical exertion activities that are representative of the events intended to be monitored with the proposed method and system, enabling a corresponding dynamic physiological response model to be created. The motion tracking system and physiological response model can then be used to predict the physiological response to physical exertion events under a prescribed framework, including applications during real-time event monitoring.
    Type: Application
    Filed: May 13, 2021
    Publication date: May 12, 2022
    Applicant: Salutron, Inc.
    Inventor: Lino Velo
  • Publication number: 20220142511
    Abstract: Automated systems and methods are presented for determining the physiological response of human or suitable animal subjects to physical exertion. The methods and systems can include monitoring sensors that capture the motion of the subject along with corresponding physiological data, and can track such motion for the duration of a period of physical exertion. The system is able to acquire an initial stream of physiological data from the subject during a range of physical exertion activities that are representative of the events intended to be monitored with the proposed method and system, enabling a corresponding dynamic physiological response model to be created. The motion tracking system and physiological response model can then be used to predict the physiological response to physical exertion events under a prescribed framework, including applications during real-time event monitoring.
    Type: Application
    Filed: May 13, 2021
    Publication date: May 12, 2022
    Applicant: Salutron, Inc.
    Inventor: Lino Velo
  • Patent number: 11291401
    Abstract: Described herein are user-wearable devices, and methods for use therewith, for monitoring for one or more types of arrhythmias based on a photoplethysmography (PPG) signal obtained using an optical sensor of a user-wearable device. A PPG based statistical and/or machine learning model is used to analyze a PPG signal, obtained using the optical sensor, to monitor for one or more types of arrhythmias including atrial fibrillation (AF). In response to detecting an arrhythmia based on the PPG signal, an electrocardiogram (ECG) signal is obtained using an ECG sensor of the user-wearable device. An ECG based statistical and/or machine learning model is used to analyze the ECG signal obtained using the ECG sensor of the user-wearable device to confirm or reject the arrhythmia detected based on the PPG signal and/or to perform arrhythmia discrimination. Obtained PPG and/or ECG signal segments can be provided to the model(s) to update the model(s).
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 5, 2022
    Assignee: Salutron, Inc.
    Inventor: Lino Velo
  • Publication number: 20200100693
    Abstract: Described herein are user-wearable devices, and methods for use therewith, for monitoring for one or more types of arrhythmias based on a photoplethysmography (PPG) signal obtained using an optical sensor of a user-wearable device. A PPG based statistical and/or machine learning model is used to analyze a PPG signal, obtained using the optical sensor, to monitor for one or more types of arrhythmias including atrial fibrillation (AF). In response to detecting an arrhythmia based on the PPG signal, an electrocardiogram (ECG) signal is obtained using an ECG sensor of the user-wearable device. An ECG based statistical and/or machine learning model is used to analyze the ECG signal obtained using the ECG sensor of the user-wearable device to confirm or reject the arrhythmia detected based on the PPG signal and/or to perform arrhythmia discrimination. Obtained PPG and/or ECG signal segments can be provided to the model(s) to update the model(s).
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Applicant: Salutron, Inc.
    Inventor: Lino Velo
  • Patent number: 10265024
    Abstract: Technology is described for a wearable sensor system including an accelerometer and a PPG optical sensor having light processing elements including at least one photodetector in at least one linear configuration sharing an axis of orientation with the accelerometer. Heart rate measurements determined from reflected light detected by a photodetector of the light processing elements in a linear configuration are co-sampled with accelerometer measurements for one of its axes sharing its orientation with the linear configuration, thus providing per axis measurements which provide more precise data points for more easily compensating for motion artifacts in heart rate data. A wrist wearable biometric monitoring device is also described which embodies the wearable sensor system and performs active motion artifact compensation.
    Type: Grant
    Filed: July 26, 2014
    Date of Patent: April 23, 2019
    Assignee: Salutron, Inc.
    Inventors: Yong Jin Lee, Lino Velo
  • Publication number: 20160022220
    Abstract: Technology is described for a wearable sensor system including an accelerometer and a PPG optical sensor having light processing elements including at least one photodetector in at least one linear configuration sharing an axis of orientation with the accelerometer. Heart rate measurements determined from reflected light detected by a photodetector of the light processing elements in a linear configuration are co-sampled with accelerometer measurements for one of its axes sharing its orientation with the linear configuration, thus providing per axis measurements which provide more precise data points for more easily compensating for motion artifacts in heart rate data. A wrist wearable biometric monitoring device is also described which embodies the wearable sensor system and performs active motion artifact compensation.
    Type: Application
    Filed: July 26, 2014
    Publication date: January 28, 2016
    Inventors: Yong Jin Lee, Lino Velo
  • Patent number: 6812126
    Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and time. The barrier can comprises a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: November 2, 2004
    Assignee: CVC Products, Inc.
    Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Randhir S. Bubber, Lino A. Velo
  • Patent number: 6645847
    Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: November 11, 2003
    Assignee: CVC Products, Inc.
    Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., David M. Leet, Sanjay Gopinath
  • Patent number: 6627995
    Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: September 30, 2003
    Assignee: CVC Products, Inc.
    Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., David M. Leet, Sanjay Gopinath
  • Patent number: 6461675
    Abstract: Adhesion of a copper film, such as a copper interconnect, to a substrate underlayer, such as a substrate diffusion barrier, is enhanced with adhesion promotion techniques. The adhesion promotion techniques can repair the interface of the copper film and the substrate to enhance adhesion of the copper film for high-yield formation of inlaid copper metal lines and plugs. For instance, thermal annealing of a seed layer, including a copper seed layer, an alloy seed layer or a reactant seed layer, can repair contamination at the interface of the seed layer and the substrate. Alternatively, the adhesion promotion techniques can avoid contamination of the interface by depositing an inert seed layer, such as a noble (e.g., platinum) or passivated metal seed layer, or by depositing the seed layer under predetermined conditions that minimize contamination of the interface, and then depositing a bulk copper layer under predetermined conditions that maximize throughput.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: October 8, 2002
    Assignee: CVC Products, Inc.
    Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., Zeming Liu, Guihua Shang
  • Publication number: 20020137332
    Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
    Type: Application
    Filed: April 1, 2002
    Publication date: September 26, 2002
    Applicant: CVC Products, Inc., a Delware corporation
    Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, David M. Leet, Sanjay Gopinath
  • Publication number: 20020102838
    Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
    Type: Application
    Filed: January 30, 2002
    Publication date: August 1, 2002
    Applicant: CVC Products, Inc., a Delaware corporation
    Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, David M. Leet, Sanjay Gopinath
  • Patent number: 6365502
    Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: April 2, 2002
    Assignee: CVC Products, Inc.
    Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., David M. Leet, Sanjay Gopinath
  • Publication number: 20020006468
    Abstract: Adhesion of a copper film, such as a copper interconnect, to a substrate underlayer, such as a substrate diffusion barrier, is enhanced with adhesion promotion techniques. The adhesion promotion techniques can repair the interface of the copper film and the substrate to enhance adhesion of the copper film for high-yield formation of inlaid copper metal lines and plugs. For instance, thermal annealing of a seed layer, including a copper seed layer, an alloy seed layer or a reactant seed layer, can repair contamination at the interface of the seed layer and the substrate. Alternatively, the adhesion promotion techniques can avoid contamination of the interface by depositing an inert seed layer, such as a noble (e.g., platinum) or passivated metal seed layer, or by depositing the seed layer under predetermined conditions that minimize contamination of the interface, and then depositing a bulk copper layer under predetermined conditions that maximize throughput.
    Type: Application
    Filed: July 10, 1998
    Publication date: January 17, 2002
    Inventors: AJIT P. PARANJPE, MEHRDAD M. MOSLEHI, LINO A. VELO, THOMAS R. OMSTEAD, DAVID R. CAMPBELL, ZEMING LIU, GUIHUA SHANG
  • Patent number: 6294836
    Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and tin. The barrier can comprise a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization in one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: September 25, 2001
    Assignee: CVC Products Inc.
    Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Randhir S. Bubber, Lino A. Velo
  • Patent number: 6204204
    Abstract: A method and apparatus are disclosed for depositing a tantalum-containing diffusion barrier, such as a TaN barrier layer, by dissolving a tantalum-bearing organometallic precursor, such as PEMAT or PDEAT, in an inert, low viscosity, high molecular weight, low volatility solvent, such as octane, heptane, decane or toluene. The precursor-solvent solution is vaporized and flowed over a substrate to deposit the barrier. The precursor solution has a viscosity substantially similar to that of the solvent by maintaining the ratio of precursor to solvent at a generally low value, such as approximately 10% precursor. The boiling point of the solvent is substantially similar to the boiling point of the precursor, such as within 50% of the precursor boiling point at one atmosphere, to enhance repeatability of barrier film quality.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: March 20, 2001
    Assignee: CVC Products, Inc.
    Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Randhir S. Bubber, Lino A. Velo
  • Patent number: 5326170
    Abstract: A method for calibrating at least one temperature sensor. A wafer (30) having calibration structures of a material having a melting point in the range of 150.degree. to 1150.degree. C. is provided. The temperature sensor is operable to detect a temperature dependent characteristic of the wafer and output a signal corresponding to the temperature depending characteristic. The power input is selectively varied and the wafer temperature is ramped for a calibration run. A wafer characteristic, such as wafer reflectance, radiance, or emissivity, is monitored. A first step change in the wafer characteristic corresponding to a wafer temperature equal to the melting point of the calibration structures is detected and a set of calibration parameters for each temperature sensor being calibrated is calculated.
    Type: Grant
    Filed: September 1, 1993
    Date of Patent: July 5, 1994
    Assignee: Texas Instruments, Incorporated
    Inventors: Mehrdad M. Moslehi, Habib Najm, Lino A. Velo
  • Patent number: 5305417
    Abstract: In a RTP reactor where wafer temperature is measured by a pyrometer assembly (32), a pyrometer assembly (50) is further provided to measure the temperature of the quartz window (30) that is situated between the wafer pyrometer assembly (32) and the wafer (16) that is being processed. During the calibration procedure (100, 120) where a thermocouple wafer is used, the measurements from the wafer pyrometer assembly (32) and the window pyrometer assembly (50) are calibrated, and pyrometer measurements and thermocouple measurements are collected and compiled into calibration tables. During actual RTP reactor operation, the data from the calibration tables and current wafer and window pyrometer measurements are used to compute corrected wafer temperature(s). The corrected wafer temperature(s) is/are then used to control the intensities of the heating lamps according to the wafer processing heating schedule.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: April 19, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Habib N. Najm, Mehrdad M. Moslehi, Somnath Banerjee, Lino A. Velo
  • Patent number: 5296385
    Abstract: Several process flows are proposed for achieving suitable wafer backside structures for integrated RTP-based device processing. The wafer backside conditions proposed here can be adapted for integrated fabrication process flows based on multiple integrated single-wafer and rapid thermal processing (RTP) cycles. These backside conditions ensure repeatable RTP uniformity and accurate pyrometry calibrations and measurements. The use of a highly doped layer near the wafer backside ensures negligible infrared transmission and repeatable RTP-based process uniformity, both for the high-temperature and the lower temperature RTP-based processes such as low-pressure chemical-vapor deposition of silicon. Two backside layers are used (oxide and nitride) to prevent dopant outdiffusion and backside oxide growth due to thermal oxidation. Moreover, the backside silicon nitride layer preserves uniform backside emissivity throughout the entire flow.
    Type: Grant
    Filed: March 3, 1992
    Date of Patent: March 22, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Mehrdad M. Moslehi, John Kuehne, Lino Velo