Abstract: An apparatus includes a processor, a memory communicatively coupled to the processor, an acceleration framework circuit communicatively coupled to the memory and the processor, and a device driver. The device driver is configured to receive a request for data manipulation by a software defined storage (SDS) application. The device driver is configured to determine whether the request for data manipulation can be offloaded from the processor to the acceleration framework circuit. The device driver is configured to, based upon the determination of whether the request for data manipulation can be offloaded from the processor to the acceleration framework circuit, selectively cause the request to be executed by the acceleration framework circuit or the SDS application through execution on the processor.

Abstract: An apparatus includes a processor, a memory communicatively coupled to the processor, an acceleration framework circuit communicatively coupled to the memory and the processor, and a device driver. The device driver is configured to receive a request for data manipulation by a software defined storage (SDS) application. The device driver is configured to determine whether the request for data manipulation can be offloaded from the processor to the acceleration framework circuit. The device driver is configured to, based upon the determination of whether the request for data manipulation can be offloaded from the processor to the acceleration framework circuit, selectively cause the request to be executed by the acceleration framework circuit or the SDS application through execution on the processor.

Abstract: A processing acceleration system including at least one gate array that performs finite field arithmetic and at least one controller that sends information to the gate array(s) upon a determination that sending the information, performing the finite field arithmetic by the gate array(s), and sending results of the finite field arithmetic to at least one destination is more efficient than general-purpose computing processor(s) performing the finite field arithmetic and sending the results to the at least one destination. The gate array(s) may include field programmable gate array(s), and the destination(s) may include the general-purpose computing processor(s) or storage devices. The finite field arithmetic may include galois field arithmetic such as modular arithmetic, for example as may be used with respect to erasure coding for storage device(s).