Abstract: A voltage regulator and method. The voltage regulator includes a first amplifier having: a first input couplable to a reference voltage; a second input coupled to a feedback path; a current mirror; first and second branches coupled to an input and output of the current mirror. A node of the second branch forms an output of the first amplifier. The voltage regulator includes a second amplifier comprising a transistor having: a first terminal couplable to a supply voltage; a gate coupled to the output of the first amplifier; and a second terminal coupled to an output of the voltage regulator. The feedback path is coupled to the output of the voltage regulator. The voltage regulator includes a compensation network having at least one passive component to reduce variations in an output current of the voltage regulator caused by the parasitic capacitance of the transistor and variations in the supply voltage.

Abstract: A signal processor and method. The signal processor includes a signal current path. The signal processor includes a transconductor. The transconductor has an input operable to receive an input voltage of the signal processor. The transconductor also has an output operable to output a current based on the input voltage. The signal processor also includes a processing stage coupled to the output of the transconductor to receive and process the current outputted by the transconductor. The signal processor further includes a current replicator operable to generate a replica current proportional to the current outputted by the transconductor. The signal processor also includes a comparator operable to compare an output of the current replicator with a reference. The signal processor further includes a current limiter operable to limit the current outputted by the transconductor based on the comparison of the output of the current replicator with the reference.

Abstract: A time constant calibration circuit and method. The circuit comprises a resistor, a capacitor, an amplifier, a first switch and a second switch. The resistance of the resistor and/or the capacitance of the capacitor is variable. A first terminal of the resistor, a first terminal of the capacitor and a first input of the amplifier are coupled to a common node, which is coupleable to a reference current source. A second input of the amplifier is coupleable to a reference voltage. An output of the amplifier is coupled to a second terminal of the resistor and a second terminal of the capacitor. The circuit can perform a calibration process comprising one or more calibration cycles in which the switches route a reference current through the resistor in a first phase and through the capacitor in a second phase. The resistance and/or the capacitance is adjusted between calibration cycles.

Abstract: A time constant calibration circuit and method. The circuit comprises a resistor, a capacitor, an amplifier, a first switch and a second switch. The resistance of the resistor and/or the capacitance of the capacitor is variable. A first terminal of the resistor, a first terminal of the capacitor and a first input of the amplifier are coupled to a common node, which is coupleable to a reference current source. A second input of the amplifier is coupleable to a reference voltage. An output of the amplifier is coupled to a second terminal of the resistor and a second terminal of the capacitor. The circuit can perform a calibration process comprising one or more calibration cycles in which the switches route a reference current through the resistor in a first phase and through the capacitor in a second phase. The resistance and/or the capacitance is adjusted between calibration cycles.

Abstract: A voltage regulator and method. The voltage regulator includes a first amplifier having: a first input couplable to a reference voltage; a second input coupled to a feedback path; a current mirror; first and second branches coupled to an input and output of the current mirror. A node of the second branch forms an output of the first amplifier. The voltage regulator includes a second amplifier comprising a transistor having: a first terminal couplable to a supply voltage; a gate coupled to the output of the first amplifier; and a second terminal coupled to an output of the voltage regulator. The feedback path is coupled to the output of the voltage regulator. The voltage regulator includes a compensation network having at least one passive component to reduce variations in an output current of the voltage regulator caused by the parasitic capacitance of the transistor and variations in the supply voltage.

Abstract: A signal processor and method. The signal processor includes a signal current path. The signal processor includes a transconductor. The transconductor has an input operable to receive an input voltage of the signal processor. The transconductor also has an output operable to output a current based on the input voltage. The signal processor also includes a processing stage coupled to the output of the transconductor to receive and process the current outputted by the transconductor. The signal processor further includes a current replicator operable to generate a replica current proportional to the current outputted by the transconductor. The signal processor also includes a comparator operable to compare an output of the current replicator with a reference. The signal processor further includes a current limiter operable to limit the current outputted by the transconductor based on the comparison of the output of the current replicator with the reference.

Abstract: In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.

Abstract: In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.

Abstract: In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.

Abstract: Symmetrical eight-shaped balun (BALanced-to-UNbalanced converter) comprising a first and second eye, each eye comprising conducting tracks forming turns. The eyes comprise an equal number of primary turns that form a first conducting path from a first terminal to a second terminal, in which in operation electrical current flows in a first direction in a first eye and in a second direction in a second eye. Moreover, the eyes further comprise an equal number of secondary turns that form a second conducting path from a third terminal to a fourth terminal, in which in operation electrical current flows in a first direction in a first eye and in a second direction in a second eye. The geometrical and electrical middle points of primary and secondary turns are all superposed and further are located in the same plane.

Abstract: The invention relates to an electric device including an electric element, the electric element comprising a first electrode (104) having a first surface (106) and a pillar (108), the pillar extending from the first surface in a first direction (110), the pillar having a length measured from the first surface parallel to the first direction, the pillar having a cross section (116) perpendicular to the first direction and the pillar having a sidewall surface (120) enclosing the pillar and extending in the first direction, characterized in—that, the pillar comprises any one of a score (124) and protrusion (122) extending along at least part of the length of the pillar for giving the pillar (108) improved mechanical stability. The electrode allows electrical elements such as capacitors, energy storage devices or diodes to be made with improved properties in a cost effective way.

Abstract: In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.

Abstract: Symmetrical eight-shaped balun (BALanced-to-UNbalanced converter) comprising a first and second eye, each eye comprising conducting tracks forming turns. The eyes comprise an equal number of primary turns that form a first conducting path from a first terminal to a second terminal, in which in operation electrical current flows in a first direction in a first eye and in a second direction in a second eye. Moreover, the eyes further comprise an equal number of secondary turns that form a second conducting path from a third terminal to a fourth terminal, in which in operation electrical current flows in a first direction in a first eye and in a second direction in a second eye. The geometrical and electrical middle points of primary and secondary turns are all superposed and further are located in the same plane.

Abstract: The invention relates to an electric device including an electric element, the electric element comprising a first electrode (104) having a first surface (106) and a pillar (108), the pillar extending from the first surface in a first direction (110), the pillar having a length measured from the first surface parallel to the first direction, the pillar having a cross section (116) perpendicular to the first direction and the pillar having a sidewall surface (120) enclosing the pillar and extending in the first direction, characterized in—that, the pillar comprises any one of a score (124) and protrusion (122) extending along at least part of the length of the pillar for giving the pillar (108) improved mechanical stability. The electrode allows electrical elements such as capacitors, energy storage devices or diodes to be made with improved properties in a cost effective way.

Abstract: An electronic circuit for providing a logic gate function includes a differential signal input, a combining stage, a discriminating stage and a differential signal output. The discriminating stage includes four transistors each having first electrodes and second electrodes and a respective gate electrode. The first electrodes of the four transistors are connected to a common node. The combining stage is arranged to convert differential input signals into gate signals applied to the gate electrodes of some of the four transistors respectively.

Abstract: The invention relates to an electronic circuit comprising differential signal input means, a combining stage, a discriminating stage and differential signal output means. The discriminating stage comprises four transistors (Q8, Q9, Q10, Q11) each having first electrodes (83, 93, 103, 113) and second electrodes (81, 91, 101, 111) and a respective gate electrode (82, 92, 102, 112). The first electrodes of said four transistors are connected to a common node. The combining stage is arranged to convert differential input signals into gate signals applied to the gate electrodes of some of said four transistors respectively.

Abstract: The invention relates to a switching device comprising programmable compensation means which are associated with the input/output connections for inverting the polarity of the input/output connections when said connections present a polarity inversion which is inherent in the conception of the circuits.

Abstract: This amplifier is intended for amplifying variable signals superimposed on a continuous signal. This continuous signal serves in particular for biasing a component, a magnetoresistive resistor used as a hard disk reading head. To avoid the harmful effects of a sudden fluctuation in the continuous signal, this amplifier comprises a set of switchable reactive elements (70) for acting on said transfer function and a bias drift compensation circuit (80) for controlling the switching of said switchable elements with a view to anticipating the effects of said fluctuation.

Abstract: This amplifier is intended for amplifying variable signals superimposed on a continuous signal. This continuous signal serves in particular for biasing a component, a magnetoresistive resistor used as a hard disk reading head. To avoid the harmful effects of a sudden fluctuation in the continuous signal, this amplifier comprises a set of switchable reactive elements (70) for acting on said transfer function and a bias drift compensation circuit (80) for controlling the switching of said switchable elements with a view to anticipating the effects of said fluctuation.

Abstract: The present invention relates to an amplifier CD including a first and a second transistor T1 and T2, connected in series between a power supply terminal VCC and ground terminal. According to the invention the transfer terminal of the first transistor T1 is connected to the bias terminal of the second transistor T2 and forms an input of the amplifier CD, the bias terminal of the first transistor T1 being connected to a reference potential terminal. An amplifier CD in accordance with the invention has low input impedance and a low common-mode output level.