Abstract: A scan diagnosis analysis method and system therein utilizes clusters of scan failure callouts. According to at least one embodiment of the present disclosure, better detection of non-random failures can be enabled by utilizing a database of scan failure callouts and forming meaningful clusters or sets of scan failure callouts. Clusters can be formed by rules allowing combination of scan failure callouts having common or connected network locations or layout features.

Abstract: Disclosed techniques for performing a multiple patterning consistency analysis of an integrated circuit design identify, in a standard cell array of the integrated circuit design, a set of standard cells for multiple patterning consistency analysis. The technique may also identify cell groups in the set where all of the cells in a cell group share a common multiple patterning orientation. The technique may identify unused elements in the standard cell array that are associated with or otherwise available for use in shifting at least some of the standard cells. The technique may shift the unused elements with respect to the cell groups, e.g., insert an unused element between a preferred orientation cell group and a non-preferred orientation cell group to shift the non-preferred group by one standard cell array element and thereby change the multiple patterning orientation of the cell group.

Abstract: An instantiation of a standard cell is placed at a location of a device design. The standard cell includes a designation identifying a sensitive feature of the standard cell. An instantiation of a filler cell is placed at a selective location of the device design based on the designation.

Abstract: A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned gate material overlies the active device region between first and second portions of the boundary. The patterned gate material defines a channel within the active device region, the gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary. The channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, further being characterized by gate length dimension tapering on both ends of the channel.

Abstract: An instantiation of a standard cell is placed at a location of a device design. The standard cell includes a designation identifying a sensitive feature of the standard cell. An instantiation of a filler cell is placed at a selective location of the device design based on the designation.

Abstract: A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned gate material overlies the active device region between first and second portions of the boundary. The patterned gate material defines a channel within the active device region, the gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary. The channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, further being characterized by gate length dimension tapering on both ends of the channel.

Abstract: A method and apparatus are described for determining an accurate yield prediction for an integrated circuit by combining conventional yield loss analysis (such as extracted from physical dimension information concerning a circuit layout) with extracted electrical sensitivity and/or functional sensitivity information for circuit elements (such as nets connecting logic blocks or other signal lines) to obtain an actual performance-based probability of failure (POF) for the overall circuit.

Abstract: A semiconductor device includes an active semiconductor material. A transistor gate overlies a first portion of the active semiconductor material. A second portion intersects the first portion at a corner which is distorted during manufacture resulting in rounding of the corner. The active semiconductor material extends into the corner to create a concave corner. To reduce the corner rounding, a compensation feature extends from a first edge of the first portion by an amount less than needed to provide an electrical contact structure on the compensation feature. The feature is positioned laterally further away from the corner than the overlying transistor gate. The compensation feature is positioned from the corner by a dimension that is within 0.4 to 0.6 of the wavelength of light used to image features of the semiconductor device. Due to optical distortion the compensation feature itself has a nonlinear shape.

Abstract: A method for making a field emission cathode structure includes forming a ballast layer over a column metal layer, forming a dielectric layer over the ballast layer, forming a line metal layer over the dielectric layer, forming a trench in the line metal layer and the dielectric layer, the trench extending to the ballast layer, and forming a sidewall spacer and a sidewall blade adjacent a sidewall of the trench, where the sidewall spacer is between the dielectric layer and the sidewall blade, and where the conformal spacer is recessed as compared to the sidewall blade such that a gap is present between the sidewall blade and the line metal layer.

Abstract: A method and apparatus are described for determining an accurate yield prediction for an integrated circuit by combining conventional yield loss analysis (such as extracted from physical dimension information concerning a circuit layout) with extracted electrical sensitivity and/or functional sensitivity information for circuit elements (such as nets connecting logic blocks or other signal lines) to obtain an actual performance-based probability of failure (POF) for the overall circuit.