Abstract: Systems, methods, and apparatus are described that enable an I3C master device to support I2C clock stretch used by I2C devices connected to an I3C bus. A method performed at a master device includes enabling a line driver to drive a clock wire of the serial bus in accordance with a clock signal and when the master device is configured for a first mode of operation, enabling the line driver to drive the clock wire to a first voltage level when the clock signal is in a first signaling state and when the master device is configured for a second mode of operation, and disabling the line driver when the clock signal is in a second signaling state in the second mode of operation. A resistor pulls the clock wire to a second voltage level when the clock signal is in the second signaling state.

Abstract: SoundWire-based embedded debugging in an electronic system is provided. In this regard, in one aspect, a SoundWire slave circuit receives a SoundWire data input signal over a SoundWire bus including two physical wires. The SoundWire data input signal includes a plurality of debug configuration bits in assigned SoundWire bitslots. The SoundWire slave circuit generates a plurality debug input bits required for debugging the SoundWire slave circuit based on the debug configuration bits received in the assigned SoundWire bitslots. In another aspect, the SoundWire slave circuit returns a SoundWire data output signal, which includes a debug output bit in an assigned SoundWire bitslot, over the SoundWire bus. By receiving debugging configurations and returning debugging results over the SoundWire bus, it is possible to debug the SoundWire slave circuit with a reduced number of physical pins, thus helping to reduce the overall pin count and footprint of the electronic device.

Abstract: Data bus activation in an electronic device is provided. In one aspect, a host circuit determines a cumulative potential representing a cumulative fractional bus activation vote on a data line(s) in the data bus. The host circuit activates the data bus when the cumulative potential is greater than a configurable bus activation threshold. In another aspect, a device circuit(s) determines a selected signal strength threshold that is less than determined signal strength of an incoming signal. Accordingly, the device circuit(s) asserts a fractional potential corresponding to the selected signal strength threshold on the data line(s) as a fractional bus activation vote in the cumulative fractional bus activation vote. By activating the data bus based on the cumulative fractional bus activation vote, the host circuit can support timely data bus activation while preventing the data bus from being falsely activated, thus improving robustness of data bus activation in the electronic device.

Abstract: Selective processor wake-up in an electronic device is provided. In one aspect, a master circuit in an electronic device is communicatively coupled to a data bus that includes a primary data line and a plurality of secondary data lines preconfigured to identify a plurality of processors in the electronic device, respectively. The master circuit detects a processor wake-up trigger(s) asserted on a secondary data line(s) and wakes up a target processor(s) identified by the secondary data line(s). In another aspect, a client circuit(s) identifies the secondary data line(s) preconfigured to identify the target processor(s) and asserts the processor wake-up trigger(s) on the secondary data line(s). By conveying the processor wake-up trigger(s) over the secondary data line(s) preconfigured to identify the target processor(s), it may be possible to optimize processor wake-up efficiency and responsiveness in the master circuit, thus leading to improved power consumption and battery life in the electronic device.

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

Abstract: System, methods and apparatus are described that improve link turnaround performance in a differentially driven link. A method performed at a first device coupled to a two-wire serial link includes transmitting from the first device first differentially-encoded data to a second device over the two-wire serial link during a first time period, receiving at the first device second differentially-encoded data from the second device over the two-wire serial link during a second time period, and driving by the first device both wires of the two-wire serial link to a common voltage level during a third time period, the third time period spanning a link turnaround period between the first time period and the second time period. Both wires of the two-wire serial link are driven toward the common voltage level by the second device during the third time period.

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

Abstract: Low latency transmission systems and methods for long distances in SOUNDWIRE systems are disclosed. In an exemplary aspect, a SOUNDWIRE sub-system is coupled to a long cable through a bridge. The bridge converts SOUNDWIRE signals to signals for transmission over the long cable and converts the signals from the long cable to the SOUNDWIRE signals for transmission in the SOUNDWIRE sub-system. Conversion between signal types may include concatenating signals of a similar type into a group that is serially transmitted over the long cable. Concatenation of bit slots in this manner consumes minimal overhead in bus turnaround, thereby reducing latency. In further aspects, the functionality of the bridge may be incorporated into a headset or a mobile terminal.

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

Abstract: Low latency transmission systems and methods for long distances in SOUNDWIRE systems are disclosed. In an exemplary aspect, a SOUNDWIRE sub-system is coupled to a long cable through a bridge. The bridge converts SOUNDWIRE signals to signals for transmission over the long cable and converts the signals from the long cable to the SOUNDWIRE signals for transmission in the SOUNDWIRE sub-system. Conversion between signal types may include concatenating signals of a similar type into a group that is serially transmitted over the long cable. Concatenation of bit slots in this manner consumes minimal overhead in bus turnaround, thereby reducing latency. In further aspects, the functionality of the bridge may be incorporated into a headset or a mobile terminal.

Abstract: Full bandwidth communication buses are disclosed. While primarily focused on the Serial Low-power Inter-chip Media Bus (SLIMbus) communication bus, the concepts of the present disclosure may be extended to other communication buses. Exemplary aspects of the present disclosure utilize a reserved segment distribution code and a segment length to define a Segment Interval that is better-sized relative to raw data bits. By fitting the segment interval to the size of the raw data bits, bandwidth utilization is maximized, resulting in faster effective data transfers. Completion of such efficient data transfers may allow the communication bus to spend more time in a low-power mode and thus, conserve power. Additionally, such efficient data transfers may allow for better quality in presentation of multimedia content to the user.

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

Abstract: SoundWire-based embedded debugging in an electronic system is provided. In this regard, in one aspect, a SoundWire slave circuit receives a SoundWire data input signal over a SoundWire bus including two physical wires. The SoundWire data input signal includes a plurality of debug configuration bits in assigned SoundWire bitslots. The SoundWire slave circuit generates a plurality debug input bits required for debugging the SoundWire slave circuit based on the debug configuration bits received in the assigned SoundWire bitslots. In another aspect, the SoundWire slave circuit returns a SoundWire data output signal, which includes a debug output bit in an assigned SoundWire bitslot, over the SoundWire bus. By receiving debugging configurations and returning debugging results over the SoundWire bus, it is possible to debug the SoundWire slave circuit with a reduced number of physical pins, thus helping to reduce the overall pin count and footprint of the electronic device.

Abstract: Power reduction through clock management techniques are disclosed. In one aspect, the clock management is applied to a clock signal on a SOUNDWIRE™ communication bus. In particular, a control system associated with a master device on the communication bus may evaluate frequency requirements of audio streams on the communication bus and select a lowest possible clock frequency that meets the frequency requirements. Lower clock frequencies result in fewer clock transitions and result in a net power saving relative to higher clock frequencies. In the event of a clock frequency change, the master device communicates the clock frequency that will be used prospectively to slave devices on the communication bus, and all devices transition to the new frequency at the same frame boundary. In addition to the power savings, exemplary aspects of the present disclosure do not impact an active audio stream.

Abstract: A flow control protocol for an audio bus is disclosed. In an exemplary aspect, an audio source may push content to an audio sink over one or more cascaded audio bus segments or links. The audio source will send an indication to the audio sink that data is coming, and the audio sink should manipulate the data accordingly. Conversely, the audio source may also send an indication to the audio sink that, in a particular sample-event in a particular future sample-window, no data is present and the audio sink may disregard any bits in the corresponding sample-event. In another exemplary aspect, the audio sink may request data from the audio source with a receive ready indication. The audio source then sends data in a corresponding time slot for processing by the audio sink. Likewise, the audio sink may provide an indication that the audio sink cannot accept more data through a negative receive ready indication.

Abstract: Power reduction through clock management techniques are disclosed. In one aspect, the clock management is applied to a clock signal on a SOUNDWIRE™ communication bus. In particular, a control system associated with a master device on the communication bus may evaluate frequency requirements of audio streams on the communication bus and select a lowest possible clock frequency that meets the frequency requirements. Lower clock frequencies result in fewer clock transitions and result in a net power saving relative to higher clock frequencies. In the event of a clock frequency change, the master device communicates the clock frequency that will be used prospectively to slave devices on the communication bus, and all devices transition to the new frequency at the same frame boundary. In addition to the power savings, exemplary aspects of the present disclosure do not impact an active audio stream.

Abstract: Predefined static enumeration systems and processes for dynamic enumeration buses are disclosed. In one aspect, the dynamic enumeration bus may be a SOUNDWIRE™ bus. Slave devices are provided predefined device numbers which are provided to a master. The master uses the provided predefined device number to populate an address table. By providing the predefined device numbers, an iterative enumeration process may be reduced or eliminated, saving time and/or power.

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

Abstract: System, methods and apparatus are described that improve link turnaround performance in a differentially driven link. A method performed at a first device coupled to a two-wire serial link includes transmitting from the first device first differentially-encoded data to a second device over the two-wire serial link during a first time period, receiving at the first device second differentially-encoded data from the second device over the two-wire serial link during a second time period, and driving by the first device both wires of the two-wire serial link to a common voltage level during a third time period, the third time period spanning a link turnaround period between the first time period and the second time period. Both wires of the two-wire serial link are driven toward the common voltage level by the second device during the third time period.

Abstract: Time-constrained data copying between storage media is disclosed. When an electronic device is engaged in real-time operations, multiple data blocks may need to be copied from one storage medium to another storage medium within certain time constraints. In this regard, a data port is operatively controlled by a plurality of registers of a first register bank. The plurality of registers is copied from the first register bank to a second register bank within a temporal limit and while the data port remains under control of the plurality of registers being copied. By copying the plurality of registers within the temporal limit, it is possible to prevent operational interruption in the data port and reduce bandwidth overhead associated with the register copying operation.