Patents by Inventor Lior BUBLIL

Lior BUBLIL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11816349
    Abstract: A system and apparatus for secure NVM format by pre-erase is disclosed. According to certain embodiments when an NVM does into idle mode, one or more free blocks are serially popped from a free block heap. The free block is then physically erased in an SLC mode, and then pushed to a pre-erase heap. The process is performed in both SLC and TLC partitions, in the TLC partition the block becomes hybrid SLC (HSLC). This process increases a program erase count (PEC) value of the block, maintaining device longevity. When there is a need to use a new block, it is popped from the pre-erase heap. In some cases where there is a need to use a TLC block instead of an HSLC block, an erase operation is used that converts the block from HSLC to TLC, and does not increase a PEC value for the block.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: November 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Lola Grin, Itay Busnach, Micha Yonin, Lior Bublil
  • Patent number: 11756637
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a power loss event has occurred, determine that one or more blocks are in an erased state, examine a block of the one or more blocks to determine whether the block is a SLC erased block or a TLC erased block, and place the block in a SLC pre-erase heap if the block is the SLC erased block or in a TLC pre-erase heap if the block is the TLC erased block. The controller is further configured to determine a first bit count of page0 for a SLC voltage for the block, determine a second bit count of page1 for a TLC voltage for the block, and classify the block as either a SLC erased block or a TLC erased block.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: September 12, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Michael Ionin, Lior Avital, Tomer T. Eliash, Lola Grin, Alexander Bazarsky, Itay Busnach, Lior Bublil, Mahim Gupta
  • Publication number: 20230137039
    Abstract: A system and apparatus for secure NVM format by pre-erase is disclosed. According to certain embodiments when an NVM does into idle mode, one or more free blocks are serially popped from a free block heap. The free block is then physically erased in an SLC mode, and then pushed to a pre-erase heap. The process is performed in both SLC and TLC partitions, in the TLC partition the block becomes hybrid SLC (HSLC). This process increases a program erase count (PEC) value of the block, maintaining device longevity. When there is a need to use a new block, it is popped from the pre-erase heap. In some cases where there is a need to use a TLC block instead of an HSLC block, an erase operation is used that converts the block from HSLC to TLC, and does not increase a PEC value for the block.
    Type: Application
    Filed: November 3, 2021
    Publication date: May 4, 2023
    Inventors: Lola GRIN, Itay BUSNACH, Micha YONIN, Lior BUBLIL