Patents by Inventor Lior Katzri

Lior Katzri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10218596
    Abstract: A method is described and in one embodiment includes receiving at a first network element of a communications network a first packet corresponding to a first traffic flow from a first end user device to a second end user device at a time T1; receiving at the first network element a second packet corresponding to a second traffic flow from the second end user device to the first end user device at a time T2; calculating by the first network element a difference ?1 between the time T1 and the time T2; creating at the first network element a first record including the calculated difference ?1; and providing the first record to a network collector device, wherein the network collector device compares the first record with a second record received from a second network element to determine a Round Trip Time (“RTT”) delay for the communications network.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: February 26, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Nir Ben-Dvora, Lior Katzri
  • Publication number: 20180234316
    Abstract: A method is described and in one embodiment includes receiving at a first network element of a communications network a first packet corresponding to a first traffic flow from a first end user device to a second end user device at a time T1; receiving at the first network element a second packet corresponding to a second traffic flow from the second end user device to the first end user device at a time T2; calculating by the first network element a difference ?1 between the time T1 and the time T2; creating at the first network element a first record including the calculated difference ?1; and providing the first record to a network collector device, wherein the network collector device compares the first record with a second record received from a second network element to determine a Round Trip Time (“RTT”) delay for the communications network.
    Type: Application
    Filed: February 10, 2017
    Publication date: August 16, 2018
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Nir Ben-Dvora, Lior Katzri
  • Patent number: 6643289
    Abstract: A method of notification and handling of device status changes in MPOA enabled ATM based networks. In a first method notification of changes in device status configuration are provided by selectively releasing one or more Data Direct VCs that were previously established be LECs connecting MPOA Servers and MPOA Clients. An MPOA Server, upon detecting a change to its device configuration status, releases the Data Direct VCs connecting its associated LEC to known MPSs and MPCs that are neighbors to it. All MPOA devices for which a Data Direct VC was released delete all LE_ARP cache entries associated with the ATM destination of the released Data Direct VC. In a second method, each MPOA device periodically sends keep alive messages as targetless LE_ARP messages having a time to live TLV appended. An MPOA device receiving the keep alive message, refreshes (i.e., restarts) a validation timer for each association made by the corresponding MPOA identification TLV.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: November 4, 2003
    Assignee: 3Com Corporation
    Inventors: Sarit Shani Natanson, Lior Katzri, Benny Gershon, Ronit Aizicovich
  • Patent number: 6639901
    Abstract: An apparatus for and a method of extending the ATM Forum LAN Emulation standard to support 802.1Q VLAN tagging with Independent VLAN Learning. A standard LEC entity is modified to perform the VLAN tagging method that supports Independent VLAN Learning. Since the LES may also respond to LE_ARP messages, it is optionally modified to perform the VLAN tagging method of the invention so as to provide support for 802.1Q Independent VLAN Learning. Support for 802.1Q Independent VLAN Learning is provided by adding a VLAN-ID TLV to LAN Emulation control messages such as LE_ARP and LE_REGISTER messages. The TLV added comprises the VLAN Tag Header information that is normally carried by the Ethernet frame in 802.1Q networks.
    Type: Grant
    Filed: January 24, 2000
    Date of Patent: October 28, 2003
    Assignee: 3Com Corporation
    Inventors: Lior Katzri, Opher Yaron
  • Patent number: 6633542
    Abstract: A method of controlling the route used for a flow in an environment comprising a default routing path and a shortcut path in an MPOA enabled ATM based network. A data field is added to the Ingress Cache table in the Ingress MPOA Client (I-MPC) to indicate whether the flow is to be routed through an MPOA shortcut towards the Egress MPOA Client (E-MPC) or is to be routed through the default path towards the Ingress MPOA Server (I-MPS). A first embodiment comprises a method of controlling the routing of a data flow from a source to a destination for security purposes. A second embodiment comprises a method of load sharing a plurality of data flows. A third embodiment comprises a method of learning about past MPOA resolution successes and failures and utilizing past establishment history to bypass the MPOA resolution process.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: October 14, 2003
    Assignee: 3Com Corporation
    Inventors: Sarit Shani Natanson, Benny Gershon, Lior Katzri
  • Patent number: 6606321
    Abstract: A method of establishing calls between an ingress MPC (the calling party) and an egress MPC (the called party) in MPOA enabled ATM based networks. The call establishment method utilizes the call request SETUP, CONNECT and CONNECT_ACK messages in creating the shortcut VCC between ingress and egress MPCs. The calling party is adapted to send a READY_IND message in a reliable manner to the called party indicating that it is ready to receive frames over the shortcut VCC. The called party starts sending data over the shortcut VCC only when it knows that the calling party is ready. The called party knows the calling party is ready upon receipt of a READY_IND message or at least one data frame on the shortcut VCC. The calling party knows that the called party is ready to receive frames when it receives the CONNECT message. Since the READY_IND message sent by the calling party may get lost, the calling party is adapted to re-send the READY_IND message repeatedly until it is certain the called party has received it.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: August 12, 2003
    Assignee: 3Com Corporation
    Inventors: Sarit Shani Natanson, Lior Katzri, Benny Gershon, Dror Goldstein
  • Patent number: 6563830
    Abstract: An apparatus for and a method of implementing multicast registration in an ATM based ELAN. The present invention provides a mechanism for a LEC to register to receive all multicast group traffic flows without requiring the LEC to generate a separate request for each multicast MAC address. The mechanism of the present invention provides means for a LEC to register to receive all multicast flows by defining an ‘all_multicast’ TLV and including this TLV in the LE_REGISTER_REQUEST request message sent by the LEC. The LEC, LES and SMS are modified to perform the multicast registration/unregistration method of the present invention. The LEC generates the LE_REGISTER_REQUEST message and includes the all_multicast TLV indicating that the LEC desires to receive all multicast traffic flows in the ELAN. The LES, upon receipt of such an all_multicast TLV, adds the LEC to its list of LECs to receive all multicast traffic and communicates the related information to the SMS.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: May 13, 2003
    Assignee: 3Com Corporation
    Inventors: Benny Gershon, Lior Katzri, Yuri Shwartsburd
  • Patent number: 5596764
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: January 21, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Gideon Intrater, Lior Katzri, Omri Viner, Raya Levitan, Yehezkel Tzadik
  • Patent number: 5592677
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: January 7, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Amos Intrater, Andy Birenbaum, Gideon Intrater, Iddo Carmon, Ilan Shimony, Itael Fraenkel, Lev Epstein, Lior Katzri, Omri Viner, Raya Levitan, Ronny Cohen, Sidi Yomtov, Yehezkel Tzadik, Zvi Greenfeld, Israel Greiss, Oved Oz, Yachin Afek, Meir Tsadik, Moshe Doron, Alberto Sandbank
  • Patent number: 5590357
    Abstract: An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: December 31, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Amos Intrater, Andy Birenbaum, Gideon Intrater, Iddo Carmon, Ilan Shimony, Itael Fraenkel, Lev Epstein, Lior Katzri, Omri Viner, Raya Levitan, Ronny Cohen, Sidi Yomtov, Yehezkel Tzadik, Zvi Greenfeld, Israel Greiss, Oved Oz, Yachin Afek, Meir Tsadik, Moshe Doron, Alberto Sandbank