Patents by Inventor Lisa M. Studzinski

Lisa M. Studzinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6291272
    Abstract: A process for fabricating a microelectronic structure. The process comprises processing a metal carrier having a top surface and a bottom surface, wherein the top surface and the bottom surface are processed to promote adhesion, forming a dielectric layer around the metal carrier, wherein the dielectric layer substantially covers the top surface and the bottom surface of the metal carrier, and applying a first patterned layer of conductive material to the microelectronic structure. In one preferred embodiment, the process further comprises comprising sintering the metal carrier, the dielectric layer, and the first patterned layer of conductive material. In one preferred embodiment, the process further comprises forming a via hole through the metal carrier before the forming of the dielectric layer around the metal carrier, wherein the forming of the dielectric layer comprises forming the dielectric layer inside the via hole.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: September 18, 2001
    Assignee: International Business Machines Corporation
    Inventors: Ajay P. Giri, John U. Knickerbocker, David C. Long, Subhash L. Shinde, Lisa M. Studzinski, Rao V. Vallabhaneni
  • Patent number: 6261467
    Abstract: A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: July 17, 2001
    Assignee: International Business Machines Corporation
    Inventors: Ajay P. Giri, Sundar M. Kamath, Daniel P. O'Connor, Rajesh B. Patel, Herbert I. Stoller, Lisa M. Studzinski, Paul R. Walling
  • Patent number: 6096565
    Abstract: A multilayer ceramic substrate electronic component is provided having high temperature superconductor material circuitry. The high temperature superconductor material is preferably yttrium-barium-copper-oxide and is encased within a noble metal such as silver or gold when forming the surface circuitry or filling of the vias. The noble metal layers preferably have through-openings to enable direct connection of circuitry to the encased superconductor layer. A method is also provided for fabricating such multilayer ceramic substrate electronic components.
    Type: Grant
    Filed: March 9, 1999
    Date of Patent: August 1, 2000
    Assignee: International Business Machines Corporation
    Inventors: David B. Goland, Richard A. Shelleman, Subhash L. Shinde, Lisa M. Studzinski, Rao V. Vallabhaneni
  • Patent number: 6037044
    Abstract: A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer.
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: March 14, 2000
    Assignee: International Business Machines Corporation
    Inventors: Ajay P. Giri, Sundar M. Kamath, Daniel P. O'Connor, Rajesh B. Patel, Herbert I. Stoller, Lisa M. Studzinski, Paul R. Walling
  • Patent number: 6002951
    Abstract: A multilayer ceramic substrate electronic component is provided having high temperature superconductor material circuitry. The high temperature superconductor material is preferably yttrium-barium-copper-oxide and is encased within a noble metal such as silver or gold when forming the surface circuitry or filling of the vias. The noble metal layers preferably have through-openings to enable direct connection of circuitry to the encased superconductor layer. A method is also provided for fabricating such multilayer ceramic substrate electronic components.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: December 14, 1999
    Assignee: International Business Machines Corporation
    Inventors: David B. Goland, Richard A. Shelleman, Subhash L. Shinde, Lisa M. Studzinski, Rao V. Vallabhaneni