Patents by Inventor Lisa Sugiura

Lisa Sugiura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6242761
    Abstract: In order to remove the problems in conventional nitride compound semiconductor laser structures, namely, high operation voltage caused by a high resistance in a p-type layer and a high contact resistance of an electrode, damage to the crystal caused by dry etching, insufficient current injection, and the need for a high current density, a nitride compound semiconductor light emitting device has current blocking layers made of n-type B(1−x−y−z)InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1) single crystal containing an oxide of a predetermined metal, carbon and impurities exhibiting p-type and n-type conductivity, or i-type B(1−x−y−z)InxAlyGazN (0≦x≦1, 0≦y≦1, 0≦z≦1) single crystal in which carriers are inactivated by hydrogen or oxygen to realize an internal current blocking structure without the need for dry etching.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: June 5, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetoshi Fujimoto, John Rennie, Masahiro Yamamoto, Masayuki Ishikawa, Shinya Nunoue, Lisa Sugiura
  • Patent number: 6204084
    Abstract: The present invention provides a nitride system semiconductor device which decreases in cost and improves productivity without heat treatment after the growth and which increases lifetime and reliability by enhancing the quality of a p-type conductive layer, and a method for manufacturing the nitride system semiconductor device. The nitride system semiconductor device has a multilayer structure of an n-type InxGayAlzB1-x-y-zNmPnAs1-m-n (0≦x, 0≦y 0≦z, 0≦x+y+z≦1, 0<m, 0≦n, 0<m+n≦1) layer, a p-type InxGayAlzB1-x-y-zNmPnAs1-m-n (0≦x, 0≦y, 0≦z, 0≦x+y+z≦1, 0<m, 0<n, 0<m+n≦1) layer, and an electrode 22 formed on a substrate. The oxygen concentration of the surface of the p-type InxGayAlzB1-x-y-zNmPnAs1-m-n layer is 5×1018 cm−3 or lower.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: March 20, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Lisa Sugiura, Mariko Suzuki, Kazuhiko Itaya, Hidetoshi Fujimoto, Johji Nishio, John Rennie, Hideto Sugawara
  • Patent number: 6147364
    Abstract: A gallium nitride (GaN)-based semiconductor device comprises a substrate, a single-crystal layer consisting mainly of GaN with a magnesium (Mg) concentration of N.sub.bg1 cm.sup.-3, the single-crystal layer being provided near the substrate and having a thickness of d.sub.1 .mu.m, and a semiconductor layer consisting mainly of Ga.sub.1-x Al.sub.x N having an Al composition x of at least 0.02 and not higher than 1 and having a thickness of d.sub.2 .mu.m. The single-crystal layer is situated between the substrate and the semiconductor layer, and Mg is added to the semiconductor layer at a concentration of N.sub.Mg cm.sup.-3. The Al composition x, the concentration N.sub.Mg, the concentration N.sub.bg1, the thickness d.sub.1 and the thickness d.sub.2 have the following relationshipd.sub.1 /(1600.times.x)<d.sub.2 <3.6.times.10.sup.-3 .times.logN/(x+0.02)+0.02wherein when N.sub.Mg >N.sub.bg1, N cm.sup.-3 =N.sub.Mg -N.sub.bg1, and when N.sub.Mg .ltoreq.N.sub.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: November 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Itaya, Hidetoshi Fujimoto, Johji Nishio, Mariko Suzuki, Lisa Sugiura
  • Patent number: 6015979
    Abstract: Nitride-based semiconductor element comprises a first layer, a mask formed on the first layer and has a plurality of opening portions, a nitride-based compound semiconductor layer formed on the mask, the nitride-based compound semiconductor layer including a first region having threading dislocations produced in such a manner that, in approximately a middle portion between two adjacent ones of the plurality of opening portions in the mask, a plurality of dislocations extend in a vertical direction to a surface of the mask, and a second region which comprises portions other than the middle portions and free from the dislocations, and a desired element structure formed on the semiconductor layer.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: January 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Lisa Sugiura, Masayuki Ishikawa, Shinya Nunoue, Masaaki Onomura, Masahiro Yamamoto
  • Patent number: 5932896
    Abstract: The present invention provides a nitride system semiconductor device which decreases cost and improves productivity without heat treatment after the growth and which increases in lifetime and reliability by enhancing the quality of a p-type conductive layer, and a method for manufacturing the nitride system semiconductor device. The nitride system semiconductor device has a multilayer structure of an n-type In.sub.x Ga.sub.y Al.sub.z B.sub.1-x-y-z N.sub.m P.sub.n As.sub.1-m-n (0.ltoreq.x, 0.ltoreq.y, 0.ltoreq.z, 0.ltoreq.x+y+z.ltoreq.1, 0<m, 0.ltoreq.n, 0<m+n.ltoreq.1) layer, a p-type In.sub.x Ga.sub.y Al.sub.z B.sub.1-x-y-z N.sub.m P.sub.n As.sub.1-m-n (0.ltoreq.x, 0.ltoreq.y, 0.ltoreq.z, 0.ltoreq.x+y+z.ltoreq.1, 0<m, 0.ltoreq.n, 0<m+n.ltoreq.1) layer, and an electrode 22 formed on a substrate. The oxygen concentration of the surface of the p-type In.sub.x Ga.sub.y Al.sub.z B.sub.1-x-y-z N.sub.m P.sub.n As.sub.1-m-n layer is 5.times.10.sup.18 cm.sup.-3 or lower.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: August 3, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Lisa Sugiura, Mariko Suzuki, Kazuhiko Itaya, Hidetoshi Fujimoto, Johji Nishio, John Rennie, Hideto Sugawara
  • Patent number: 5903017
    Abstract: A gallium nitride (GaN)-based semiconductor device comprises a substrate, a single-crystal layer consisting mainly of GaN with a magnesium (Mg) concentration of N.sub.bg1 cm.sup.-3, the single-crystal layer being provided near the substrate and having a thickness of d.sub.1 .mu.m, and a semiconductor layer consisting mainly of Ga.sub.1-x Al.sub.x N having an Al composition x of at least 0.02 and not higher than 1 and having a thickness of d.sub.2 .mu.m. The single-crystal layer is situated between the substrate and the semiconductor layer, and Mg is added to the semiconductor layer at a concentration of N.sub.Mg cm.sup.-3. The Al composition x, the concentration N.sub.Mg, the concentration N.sub.bg1, the thickness d.sub.1 and the thickness d.sub.2 have the following relationshipd.sub.1 /(1600.times.x)<d.sub.2 <3.6.times.10.sup.-3 .times.logN/(x+0.02)+0.02wherein when N.sub.Mg >N.sub.bg1, N cm.sup.-3 =N.sub.Mg -N.sub.bg1, and when N.sub.Mg .ltoreq.N.sub.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: May 11, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Itaya, Hidetoshi Fujimoto, Johji Nishio, Mariko Suzuki, Lisa Sugiura