Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices and multilayer inner spacers for GAA devices are described. The multilayer inner spacer comprises an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of a substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. In some embodiments, the methods are performed in situ in an integrated deposition and etch processing system.

Abstract: A computer-implemented method for recommending a best driver to get best vehicle rental and insurance costs. The method builds a framework of a group of multiple driving candidates to select from to be a driver of a rental vehicle. The method further determines a driving score based on the collected set of data and generates an aggregate ranking of each of the multiple driving candidates based on the driving score. The method further computes an insurance cost for each of the multiple driving candidates based on the driving score and calculates a vehicle rental and insurance cost for each of the multiple driving candidates, based on the driving score. The method further ranks each of the multiple driving candidates based on the respective calculated vehicle rental cost and insurance cost and recommends a highest ranked candidate as the best driver to receive the best vehicle rental and insurance costs.

Abstract: A computer-implemented method, according to one implementation, includes: monitoring requests received for an AI interface prompt in real-time, and determining whether one or more of the requests violate compliance metrics. Risk scores are calculated for requests determined as violating the compliance metrics. The requests determined as violating the compliance metrics are updated by implementing protective measures correlated with the calculated risk scores. Moreover, the updated requests are sent to the AI interface prompt.

Abstract: An electronic device may include a display having an array of light-emitting diodes mounted to a driver die with driver circuitry for controlling the light-emitting diodes. The diodes may include contact pads. Contact pads for one of the diode terminals (e.g., the anodes or the cathodes) may be individually addressable, whereas the other diode terminals may share a common contact pad. The individually addressable contact pads and the common contact pad may be vertically stacked to improve thermal dissipation. The common contact pad may be interposed between the driver die and the individually addressable contact pads. Alternatively, the individually addressable contact pads may be interposed between the driver die and the common contact pad. Each LED array may have a dedicated driver die or one driver die may be shared between multiple LED arrays. A single LED array may include LEDs of multiple different colors.

Abstract: A display panel and a display device are disclosed. The display panel includes a first substrate, a second substrate, and a liquid crystal layer disposed therebetween. The first substrate includes a first base and a planarization layer disposed on a side of the first substrate adjacent to the liquid crystal layer. A side of the planarization layer adjacent to the liquid crystal layer includes a textured structure, which includes at least one groove path. The first substrate further includes a bottom edge. An extending direction of the at least one groove path forms an included angle with the bottom edge, the included angle being greater than or equal to 45 degrees and less than or equal to 135 degrees. A liquid crystal material in the liquid crystal layer diffuses along the extending direction of the groove path through the groove path based on capillary phenomenon.

Abstract: An example operation may include one or more of storing an index that comprises identifiers of role-based access privileges for a plurality of users with respect to a database, receiving a database query associated with a user from a software program, identifying data records within the database that the user has permission to access based on database accessibility rights of the user stored within the index, prior to execution of the database query, loading the identified data records into the memory and filtering out other data records from the database which the user does not have permission to access, and executing the database query on the identified data records loaded from the database and returning query results from the execution to the software program.

Abstract: Disclosed are a thin film transistor structure, a display panel and a display device. The thin film transistor structure includes a base, a source electrode, a drain electrode configured to connect to a pixel electrode and a grid electrode. The source electrode, the drain electrode and the grid electrode are provided on the base. and a channel is formed between the source electrode and the drain electrode. The thin film transistor structure further includes an insulating layer and a slow-release electrode. The insulating layer is provided on a side of the source electrode and the drain electrode, and filled in the channel. The slow-release electrode is provided in the insulating layer. At least a part of the slow-release electrode is provided inside the channel.

Abstract: A terminal is disclosed including a selection unit that selects first resource candidates for sidelink transmission based on monitoring in a sensing window, and specifies second resource candidates by excluding specific periodic resources that are reserved by another terminal from the first resource candidates; and a transmission unit that performs sidelink transmission using a resource selected from the second resource candidates. In another aspect, a transmission method executed by a terminal is also disclosed.

Abstract: A computer-implemented method, system and computer program product for scaling a resource of a Database as a Service (DBaaS) cluster in a cloud platform. User service requests from a service cluster to be processed by the DBaaS cluster are received. A first set of tracing data is generated by a service mesh, which facilitates service-to-service communication between the service cluster and the DBaaS cluster, from the user service requests. A second set of tracing data is generated by the DBaaS cluster from handling the user service requests. A dependency tree is then generated to discover application relationships to identify potential bottlenecks in nodes of the DBaaS cluster based on these sets of tracing data. The pod(s) of a DBaaS node are then scaled based on the dependency tree, which is used in part, to predict the utilization of the resources of the DBaaS node identified as being a potential bottleneck.

Abstract: An indication to remove one or more data in a time series database is received. A metadata index associated with the time series database is updated to indicate a soft removal of each data of the one or more data. A data hole index associated with the time series database is updated to indicate a data hole at a location of each data of the one or more data in the time series database. Responsive to an input/output rate for the time series database being below a threshold, the data hole of each data of the one or more data is optimized.

Abstract: Disclosed are a thin film transistor structure, a display panel and a display device. The thin film transistor structure includes a base, a source electrode, a drain electrode configured to connect to a pixel electrode and a grid electrode. The source electrode, the drain electrode and the grid electrode are provided on the base. and a channel is formed between the source electrode and the drain electrode. The thin film transistor structure further includes an insulating layer and a slow-release electrode. The insulating layer is provided on a side of the source electrode and the drain electrode, and filled in the channel. The slow-release electrode is provided in the insulating layer. At least a part of the slow-release electrode is provided inside the channel.

Abstract: There is disclosed in one example a heat dissipator for an electronic apparatus, including: a planar vapor chamber having a substantially rectangular form factor, wherein a second dimension d2 of the rectangular form factor is at least approximately twice a first dimension d1 of the rectangular form factor; a first fan and second fan; and a first heat pipe and second heat pipe discrete from the planar vapor chamber and disposed along first and second d1 edges of the planar vapor chamber, further disposed to conduct heat from the first and second d1 edges to the first and second fan respectively.

Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.

Abstract: An embodiment of a barrier assembly includes a housing having an aperture and a magnet at least partially disposed within the housing. A first surface of the magnet is exposed. The barrier assembly also includes a light-emitting component disposed within the aperture. Another embodiment of a barrier assembly includes a housing having a plurality of apertures formed about a perimeter of the housing. The barrier assembly also includes a magnet at least partially embedded within the housing and the magnet includes an opening formed through a center of the magnet and a plurality of light-emitting components, each light-emitting component at least partially disposed within a corresponding aperture of the plurality of apertures.

Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.

Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

Abstract: A semiconductor device is provided that includes an active region above a substrate, a first gate structure, a second gate structure, a first semiconductor structure, a second semiconductor structure and a semiconductor bridge. The first gate semiconductor and the second semiconductor structure are in the active region and between the first and the second gate structures. The first semiconductor structure is adjacent to the first gate structure and a second semiconductor structure is adjacent to the second gate structure. The semiconductor bridge is in the active region electrically coupling the first and the second semiconductor structures.

Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.

Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.