Abstract: Level shifting and amplified level shifting circuit topologies are provided that include two or more level shifting or amplified level shifting circuits. The level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted with respect to the input signals. The amplified level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted and amplified with respect to the input signals. These circuits may be utilized to form a detection circuit that detects a difference in the output signals.

Abstract: A monitoring circuit for accurately monitoring a voltage level from each of a plurality of battery cells of a battery pack includes an analog to digital converter (ADC) and a processor. The ADC is configured to accept an analog voltage signal from each of the plurality of battery cells and convert each analog voltage signal to a digital signal representative of an accurate voltage level of each battery cell. The processor receives such signals and provides a safety alert signal based on at least one of the signals. The ADC resolution may be adjustable. A balancing circuit provides a balancing signal if at least two of the digital signals indicate a voltage difference between two cells is greater than a battery cell balance threshold. An electronic device including such monitoring and balancing circuits is also provided. Various methods are also provided.

Abstract: An analog to digital converter (ADC) includes a cross switch array coupled between an input switch array and an integrator configured to alternately transfer charges from a first input capacitor and a second input capacitor to a first integration capacitor and a second integration capacitor thereby improving linearity problems caused by capacitor mismatching. The cross switch array may also be configured to transfer charges from the first input capacitor to the first integration capacitor and from the second input capacitor to the second integration capacitor during a first charge transfer time interval, and from the first input capacitor to the second integration capacitor and from the second input capacitor to the first integration capacitor during a second charge transfer time interval. A sensing system including and ADC consistent with the invention is also provided. Various methods of transferring charges in an ADC are also provided.

Abstract: An analog to digital converter (ADC) includes a cross switch array coupled between an input switch array and an integrator configured to alternately transfer charges from a first input capacitor and a second input capacitor to a first integration capacitor and a second integration capacitor thereby improving linearity problems caused by capacitor mismatching. The cross switch array may also be configured to transfer charges from the first input capacitor to the first integration capacitor and from the second input capacitor to the second integration capacitor during a first charge transfer time interval, and from the first input capacitor to the second integration capacitor and from the second input capacitor to the first integration capacitor during a second charge transfer time interval. A sensing system including and ADC consistent with the invention is also provided. Various methods of transferring charges in an ADC are also provided.

Abstract: Level shifting and amplified level shifting circuit topologies are provided that include two or more level shifting or amplified level shifting circuits. The level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted with respect to the input signals. The amplified level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted and amplified with respect to the input signals. These circuits may be utilized to form a detection circuit that detects a difference in the output signals.

Abstract: An analog to digital converter (ADC) includes a cross switch array coupled between an input switch array and an integrator configured to alternately transfer charges from a first input capacitor and a second input capacitor to a first integration capacitor and a second integration capacitor thereby improving linearity problems caused by capacitor mismatching. The cross switch array may also be configured to transfer charges from the first input capacitor to the first integration capacitor and from the second input capacitor to the second integration capacitor during a first charge transfer time interval, and from the first input capacitor to the second integration capacitor and from the second input capacitor to the first integration capacitor during a second charge transfer time interval. A sensing system including and ADC consistent with the invention is also provided. Various methods of transferring charges in an ADC are also provided.

Abstract: Disclosed is a fully differential switched-capacitor integrator which accepts a single-ended or unbalanced input signal and compensates the offset and finite gain of the operational amplifier without an extra converter circuit. The proposed circuit utilizes a special input structure which adds special capacitors to store the offset and the low frequency noise of the operational amplifier. One preferred embodiment implements the switching means as transmission gates using CMOS transistors. Clock feedthrough is prevented by providing two non-overlapping clock phases with a delayed clock each, thus avoiding clock feed-through. The invention provides a good alternative for applications such as low noise filters and sigma delta modulators.

Abstract: In the present invention is described a forward feed sigma delta modulator of higher order having automatic saturation detection and recovery. The modulator is separated into two parts which are connected together when there is no saturation, and disconnected when saturation is detected and recovery takes place. The first part contains an integrator and input output circuitry to allow continuous operation of the modulator. The second part contains additional integrators to provider for a higher order modulator and the saturation detector. The modulator can be constructed of single ended or differential switched capacitor technology, and there is a digital saturation detection scheme.