Abstract: An improved planarity when forming contact plugs by a blanket CVD deposition of a metallic matrix layer followed by etchback is achieved by performing a first etchback step to expose the surface of the dielectric material underlying the filling metal layer, while masking the top of the metal plugs with resist caps. The resist caps are formed using a mask derived by field inversion and enlargement from the actual contact mask used for defining the contact areas. With the resist caps covering the contact plugs, the filling metallic material is overetched to eliminate residues along with discontinuities from the planarity of the surface, while shielding the top of the plugs from the overetch. The masked overetch is preferably conducted under conditions of reduced anisotropy and increased selectivity in respect to the first etchback step.

Abstract: A monolithic integrated circuit of either the MOS or CMOS type comprises an intermediate layer of polycrystalline silicon, a layer of a silicide of a refractory metal overlying said polycrystalline silicon layer, and regions of preset area and preset paths formed in the polycrystalline silicon layer and the silicide layer; the preset area regions and preset paths forming respectively high resistivity resistances and low resistivity interconnection lines for an intermediate connection level.

Abstract: A method for reducing birdbeaks formed during a planox process is disclosed. On a silicon substrate (1), oxide (2) and nitride (3) are formed. The oxide and nitride are then selectively etched using a single plasma having high selectivity with respect to silicon and a photoresist mask (4). The high selectivity toward silicon is achieved by use of a CHF.sub.3 +CO.sub.2 plasma under conditions of 30:1 oxide/silicon selectivity. Field oxide regions (5) with reduced birdbeaks can then be formed.

Abstract: A nonvolatile, EPROM type memory cell, formed using a p-channel MOS device instead of an n-channel MOS device as customary according to the prior art, offers several advantages: improved programming characteristics, a relatively low gate voltage for writing, a lower power dissipation and above all compatability with the great majority of CMOS fabrication processes. An explanation of such surprising characteristics may be attributed to more favorable conditions of electric field during programming, i.e. during charging of the floating gate, in respect to those existing in the case of the conventional n-channel memory cell.

Abstract: A method is disclosed for making twin tub devices with trench isolation. The trench mask is obtained in a self-aligned manner employing tub masks that define an overlapping region at the trench. In one embodiment, the N-tub mask is defined by patterning resist (4) and polysilicon (3) overlying silicon oxide (2). The P-tub mask is defined by patterning resist (9). The oxide at the overlapping region between the tubs is removed, resulting in trench mask (2', 2") for forming trench (15). In another embodiment, the N-tub mask is defined by patterning resist (23) and silicon nitride (22). The P-tub mask is then defined by patterning resist (27) and nitride (22'). Self-aligned oxide regions (31) formed around nitride (22')serve as a trench mask for forming trench (32).

Abstract: The method provides for the formation of a layer of metal silicide on the gate layer of polycrystalline silicon and, for each transistor of the CMOS pair, the simultaneous doping of the active regions and the gate polycrystalline silicon. In the structure produced by this method, the gate electrodes are of polycrystalline silicon covered by metal silicide and the gate electrode of the n-channel transistor is doped with n-type material, while the gate electrode of the p-channel transistor is doped with p-type impurities. This enables the production of low threshold voltages for both transistors even in the case of very high integration densities.

Abstract: On the back of a wafer there are deposited firstly a gold layer and then an aluminium layer (eventually including a small silicon percent). It is finally carried out a thermic treatment at low temperature, which causes the aluminium migration towards the wafer through the gold layer.