Patents by Inventor Liying Jiang
Liying Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11939578Abstract: The present invention relates to the field of biomedicine, particularly to double-stranded RNA molecules targeting CKIP-1 and uses thereof, particularly to use of the double-stranded RNA molecules for the treatment of inflammatory diseases such as arthritis, particularly rheumatoid arthritis.Type: GrantFiled: September 14, 2021Date of Patent: March 26, 2024Assignee: BEIJING TIDE PHARMACEUTICAL CO., LTD.Inventors: Yanping Zhao, Hongjun Wang, Yuanyuan Jiang, Weiting Zhong, Jianmei Pang, Gong Li, Xiang Li, Yixin He, Liying Zhou, Yanan Liu
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Patent number: 11919918Abstract: A P2X3 and/or P2X2/3 receptor antagonist of formula (I), a pharmaceutical composition comprising the same, and a use thereof in preparing a drug for preventing or treating a disease mediated by the P2X3 and/or P2X2/3 receptor antagonist.Type: GrantFiled: May 27, 2022Date of Patent: March 5, 2024Assignee: BEIJING TIDE PHARMACEUTICAL CO., LTD.Inventors: Yanping Zhao, Hongjun Wang, Gong Li, Xiang Li, Yuanyuan Jiang, Kai Liu, Yeming Wang, Liying Zhou, Yanan Liu, Ning Shao, Fengping Xiao
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Patent number: 11682718Abstract: A vertical bipolar junction transistor may include an intrinsic base epitaxially grown on a first emitter or collector, the intrinsic base being compositionally graded, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed all-around the intrinsic base. The extrinsic base may be isolated from the first emitter or collector by a first spacer. The extrinsic base may be isolated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector, and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be made of a III-V semiconductor material.Type: GrantFiled: April 15, 2021Date of Patent: June 20, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Reznicek, Bahman Hekmatshoartabari, Tak H. Ning, Liying Jiang
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Publication number: 20220336645Abstract: A vertical bipolar junction transistor may include an intrinsic base epitaxially grown on a first emitter or collector, the intrinsic base being compositionally graded, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed all-around the intrinsic base. The extrinsic base may be isolated from the first emitter or collector by a first spacer. The extrinsic base may be isolated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector, and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be made of a III-V semiconductor material.Type: ApplicationFiled: April 15, 2021Publication date: October 20, 2022Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Tak H. Ning, Liying Jiang
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Patent number: 11282186Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.Type: GrantFiled: March 18, 2020Date of Patent: March 22, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Liying Jiang, Derrick Liu, Jingyun Zhang, Huimei Zhou
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Patent number: 11244869Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.Type: GrantFiled: April 28, 2020Date of Patent: February 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Juntao Li, Kangguo Cheng, Liying Jiang, John G. Gaudiello
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Patent number: 11177132Abstract: Methods for doping a semiconductor layer include forming a first mask on a first region of a semiconductor layer. A second region of the semiconductor layer, that is not covered by the first mask, is doped. A second mask is formed on the second region of the semiconductor layer. The first mask is etched away. The first region of the semiconductor layer is doped.Type: GrantFiled: July 3, 2019Date of Patent: November 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junli Wang, Romain Lallement, Ardasheir Rahman, Liying Jiang, Brent A. Anderson
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Patent number: 11088278Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.Type: GrantFiled: January 11, 2019Date of Patent: August 10, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huiming Bu, Liying Jiang, Siyuranga O. Koswatta, Junli Wang
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Patent number: 10903162Abstract: A method for fabricating an electronic fuse includes forming a recess within a film material to define opposed contact segments and a central fuse segment interconnecting the contact segments and altering the material of the central fuse segment of the film material to increase electrical resistance characteristics of the central fuse segment. The central fuse segment may include defects such as voids created by directing a laser at the central fuse segment as a component of a laser annealing process. Alternatively, and or additionally, the central fuse segment may include dopants implementing via an ion implantation process to increase resistance characteristics of the central fuse segment.Type: GrantFiled: March 5, 2019Date of Patent: January 26, 2021Assignee: International Business Machines CorporationInventors: Liying Jiang, Juntao Li, Chih-Chao Yang, Michael Rizzolo, Yi Song
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Publication number: 20210005459Abstract: Methods for doping a semiconductor layer include forming a first mask on a first region of a semiconductor layer. A second region of the semiconductor layer, that is not covered by the first mask, is doped. A second mask is formed on the second region of the semiconductor layer. The first mask is etched away. The first region of the semiconductor layer is doped.Type: ApplicationFiled: July 3, 2019Publication date: January 7, 2021Inventors: Junli Wang, Romain Lallement, Ardasheir Rahman, Liying Jiang, Brent A. Anderson
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Patent number: 10833180Abstract: Semiconductor devices and methods of forming the same include forming a doped drain structure having a first conductivity type on sidewalls of an intrinsic channel layer. An opening is etched in a middle of the channel layer. A doped source structure is formed having a second conductivity type in the opening of the channel layer.Type: GrantFiled: October 11, 2018Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yi Song, Junli Wang, Chi-Chun Liu, Liying Jiang
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Patent number: 10811599Abstract: A method of forming magnetic device structures and electrical contacts, including removing a portion of a second interlayer dielectric (ILD) layer to expose an underlying portion of a cap layer in a first device region, wherein the cap layer is on a first ILD layer, while leaving an ILD block in a second device region, forming a spacer layer on the exposed portion of the cap layer in the first device region, forming an electrical contact layer on the spacer layer in the first device region, forming a magnetic device layer on the electrical contact layer and ILD block, removing portions of the magnetic device layer to form a magnetic device stack on the ILD block, and removing portions of the electrical contact layer to form electrical contact pillars, wherein the portions of the electrical contact layer and portions of the magnetic device layer are removed at the same time.Type: GrantFiled: May 16, 2019Date of Patent: October 20, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Liying Jiang, Sebastian Naczas, Michael Rizzolo, Chih-Chao Yang
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Publication number: 20200286827Abstract: A method for fabricating an electronic fuse includes forming a recess within a film material to define opposed contact segments and a central fuse segment interconnecting the contact segments and altering the material of the central fuse segment of the film material to increase electrical resistance characteristics of the central fuse segment. The central fuse segment may include defects such as voids created by directing a laser at the central fuse segment as a component of a laser annealing process. Alternatively, and or additionally, the central fuse segment may include dopants implementing via an ion implantation process to increase resistance characteristics of the central fuse segment.Type: ApplicationFiled: March 5, 2019Publication date: September 10, 2020Inventors: Liying Jiang, Juntao Li, Chih-Chao Yang, Michael Rizzolo, Yi Song
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Patent number: 10756260Abstract: A method of forming magnetic device structures and electrical contacts, including removing a portion of a second interlayer dielectric (ILD) layer to expose an underlying portion of a cap layer in a first device region, wherein the cap layer is on a first ILD layer, while leaving an ILD block in a second device region, forming a spacer layer on the exposed portion of the cap layer in the first device region, forming an electrical contact layer on the spacer layer in the first device region, forming a magnetic device layer on the electrical contact layer and ILD block, removing portions of the magnetic device layer to form a magnetic device stack on the ILD block, and removing portions of the electrical contact layer to form electrical contact pillars, wherein the portions of the electrical contact layer and portions of the magnetic device layer are removed at the same time.Type: GrantFiled: May 16, 2019Date of Patent: August 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Liying Jiang, Sebastian Naczas, Michael Rizzolo, Chih-Chao Yang
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Publication number: 20200258790Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Juntao Li, Kangguo Cheng, Liying Jiang, John G. Gaudiello
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Publication number: 20200219247Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.Type: ApplicationFiled: March 18, 2020Publication date: July 9, 2020Inventors: Dechao Guo, Liying Jiang, Derrick Liu, Jingyun Zhang, Huimei Zhou
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Patent number: 10685886Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.Type: GrantFiled: December 15, 2017Date of Patent: June 16, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Juntao Li, Kangguo Cheng, Liying Jiang, John G. Gaudiello
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Patent number: 10664966Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.Type: GrantFiled: January 25, 2018Date of Patent: May 26, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Liying Jiang, Derrick Liu, Jingyun Zhang, Huimei Zhou
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Publication number: 20200119168Abstract: Semiconductor devices and methods of forming the same include forming a doped drain structure having a first conductivity type on sidewalls of an intrinsic channel layer. An opening is etched in a middle of the channel layer. A doped source structure is formed having a second conductivity type in the opening of the channel layer.Type: ApplicationFiled: October 11, 2018Publication date: April 16, 2020Inventors: Yi Song, Junli Wang, Chi-Chun Liu, Liying Jiang
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Publication number: 20190280196Abstract: A method of forming magnetic device structures and electrical contacts, including removing a portion of a second interlayer dielectric (ILD) layer to expose an underlying portion of a cap layer in a first device region, wherein the cap layer is on a first ILD layer, while leaving an ILD block in a second device region, forming a spacer layer on the exposed portion of the cap layer in the first device region, forming an electrical contact layer on the spacer layer in the first device region, forming a magnetic device layer on the electrical contact layer and ILD block, removing portions of the magnetic device layer to form a magnetic device stack on the ILD block, and removing portions of the electrical contact layer to form electrical contact pillars, wherein the portions of the electrical contact layer and portions of the magnetic device layer are removed at the same time.Type: ApplicationFiled: May 16, 2019Publication date: September 12, 2019Inventors: Lawrence A. Clevenger, Liying Jiang, Sebastian Naczas, Michael Rizzolo, Chih-Chao Yang