Abstract: An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal.

Abstract: A method and system of adaptation of a linear equalizer using a virtual decision feedback equalizer (VDFE) are disclosed. In one embodiment, a method of adjusting a setting of a linear equalizer includes determining a change to a decision feedback equalizer (DFE) tap weight value of a predefined metric according to a data signal and an error signal (e.g., the change may be generated according to an average of a specified plurality of data signals and the error signal); using the change in the DFE tap weight value to algorithmically generate a modification in a linear equalizer setting; and adjusting the linear equalizer setting. The linear equalizer is located in a feed-forward path and/or a feedback path of data transmission. The linear equalizer may be located in a transmitter and/or a receiver. The linear equalizer may be a continuous time linear equalizer and/or a Finite Impulse Response (FIR) linear equalizer.

Abstract: An apparatus includes an error sample generating circuit and an adaptation circuit. The error sample generating circuit is generally configured to generate error samples at a plurality of phases. The adaptation circuit may be configured to adjust one or more equalizer settings based upon a data sample and the error samples.

Abstract: An apparatus having a circuit is disclosed. The circuit may be configured to (i) receive an input signal from a communication channel and (ii) generate an intermediate signal by amplifying the input signal (a) by a low-frequency gain in response to an amplitude control signal and (b) by a high-frequency gain in response to a boost control signal.

Abstract: An apparatus having a transmitter is disclosed. The transmitter generally has a filter coupled to a communication channel. The transmitter may be configured to adjust the filter using information based on an estimate of one or more characteristics of the communication channel.

Abstract: An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.

Abstract: An apparatus including a receiver having a feed forward equalizer (FFE) coupled to a communication channel. The receiver may be configured to adjust the FFE using information based on an estimate of one or more characteristics of the communication channel.

Abstract: An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal.

Abstract: An apparatus having a transmitter is disclosed. The transmitter generally has a filter coupled to a communication channel. The transmitter may be configured to adjust the filter using information based on an estimate of one or more characteristics of the communication channel.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to receive a signal, where low frequency content of the signal is attenuated due to high pass filtering by a medium carrying the signal and a coupling. The second circuit may be configured to automatically set a gain of a baseline wander correction loop to restore the low frequency content in the signal based upon a sample taken from a first point in a signal pathway of the first circuit.

Abstract: An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to receive a signal, where low frequency content of the signal is attenuated due to high pass filtering by a medium carrying the signal and a coupling. The second circuit may be configured to automatically set a gain of a baseline wander correction loop to restore the low frequency content in the signal based upon a sample taken from a first point in a signal pathway of the first circuit.

Abstract: An apparatus including a bang-bang clock and data recovery module and a decision feedback equalizer. The decision feedback equalizer is coupled with the bang-bang clock and data recovery module. The apparatus is configured to reduce an effect on a settling point of the bang-bang clock and data recovery module due to coupling between the bang-bang clock and data recovery module and the decision feedback equalizer.

Abstract: An apparatus including an adder, a delay line, and a first detector. The adder may be configured to generate an input signal in response to a received signal and a feedback signal. The feedback signal may include a contribution from each of a plurality of delayed versions of the input signal. The contribution from each of the plurality of delayed versions of the input signal may be determined by a respective weight value. The delay line may be configured to generate the plurality of delayed versions of the input signal. The first detector may be configured to recover a data sample from the input signal in response to a clock signal.

Abstract: Disclosed is a method and system that adapts coefficients of taps of a Finite Impulse Response (FIR) filter to increase elimination of Inter-Symbol Interference (ISI) introduced into a digital communications signal due to distortion characteristics caused by a real-world communications channel. In the communications system there is a Finite Impulse Response (FIR) filter. The FIR filter has at least one pre and/or post cursor tap that removes pre and/or post cursor ISI from the signal, respectively. The pre/post cursor taps each have pre/post cursor coefficients, respectively, that adjusts the effect of the pre/post cursor portion of the FIR filter. The FIR filtered signal is transmitted over the channel which distorts the signal due to the changing and/or static distortion characteristics of the channel. The channel distorted signal is received at a receiver that may pass the channel distorted signal through a quantifier/decision system (e.g.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to determine values for a predefined metric for a plurality of tap positions within a range covered by a decision feedback equalizer (DFE). The values for a number of taps may be determined in parallel. The second circuit may be configured to set one or more floating taps of the DFE to tap positions based upon the values of the predefined metric. The floating taps in the decision feedback equalizer may be selected adaptively.

Abstract: Methods and apparatus are provided for decision-feedback equalization with an oversampled phase detector. A method is provided for detecting data in a receiver employing decision-feedback equalization. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and DFE transition data. One or more coefficients used for the DFE correction for the transition sample signals are adapted using the DFE transition data.

Abstract: An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate an equalized signal in response to an input signal and an equalizer parameter signal. The equalizer parameter signal generally causes a cancellation of pre-cursor inter-symbol interference from a plurality of symbols in the input signal. The second circuit may be configured to generate (i) the equalizer parameter signal, (ii) a control signal and (iii) a data output signal in response to the equalized signal. The control signal generally causes an adjustment of the equalizer parameter signal. The adjustment of the equalizer parameter signal generally causes a decrease in the pre-cursor inter-symbol interference from the symbols.

Abstract: A method of minimizing crosstalk in an IC package including (A) routing a first signal between first pads and a first trace layer in an congested area, (B) routing the first signal between the first and second trace layers in an non-congested area, (C) routing the first signal between the second trace layer and first pins in the non-congested area, (D) routing a second signal between second pads and the first trace layer in the congested area, (E) routing the second signal between the first and the second trace layers in the congested area and (F) routing the second signal between the second trace layer and second pins in the non-congested area, wherein (i) all of the first and second pins are arranged along a line and (ii) the first pins are offset from the second pins by a gap of at least two inter-pin spaces.

Abstract: An apparatus comprising an inter symbol interference (ISI) cancellation circuit and a detector circuit. The inter symbol interference (ISI) cancellation circuit may be configured to minimize ISI at data sampling and crossing sampling points in a symbol interval of an input signal. The detector circuit may be configured to generate data samples and crossing samples at the data sampling and crossing sampling points in the symbol interval of the input signal.