Patents by Inventor Ljudmil Anastasov
Ljudmil Anastasov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240142567Abstract: It is suggested to process radar signals at a first radar unit as follows: (i) receiving the radar signals via at least one receiving antenna; (ii) selecting a portion of the radar signals or of data that is based on the radar signals for further processing; and (iii) conveying a reduced amount of data to a second radar unit, wherein the reduced amount of data is based on the portion of the radar signals or of data that is based on the radar signals.Type: ApplicationFiled: October 16, 2023Publication date: May 2, 2024Inventors: Andre Roger, Markus Bichl, Ljudmil Anastasov
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Patent number: 11531085Abstract: A radar system may include a set of analog components to perform one or more radio frequency (RF) operations during an active radar phase of the radar system. The radar system may include a set of digital components to perform one or more digital processing operations during at least a digital processing phase of the radar system. The one or more digital processing operations may be performed such that performance of the one or more digital processing operations does not overlap performance of a substantive portion of the one or more RF operations.Type: GrantFiled: May 10, 2019Date of Patent: December 20, 2022Assignee: Infineon Technologies AGInventors: Witold Gora, Ljudmil Anastasov, Thomas Langschwert, Bejoy Mathews
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Patent number: 11366198Abstract: A method for processing a radar signal includes adjusting a processing clock signal, wherein the processing clock signal determines an operation period of a signal processing circuit, wherein the processing clock signal is determined based on a time window, wherein the size of the time window is determined based on the maximum time available for processing a portion of the radar signal and wherein the end of the time window is determined such that it does not occur during an active transmission portion of the radar system.Type: GrantFiled: January 24, 2020Date of Patent: June 21, 2022Assignee: Infineon Technologies AGInventors: Markus Bichl, Ljudmil Anastasov, Romain Ygnace
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Publication number: 20220060111Abstract: A power supply circuit includes: an output terminal for supplying power for a semiconductor device at the terminal; a control circuit configured to control a power level of the supplied power based on a control signal; and an input for receiving one or more timing signals, wherein the power supply circuit is configured to derive an indication for a scheduled change of a load current of the supplied power using the one or more timing signals. The power supply circuit is configured to adapt the control signal based on the indication for the scheduled change of the load current.Type: ApplicationFiled: August 17, 2021Publication date: February 24, 2022Applicant: Infineon Technologies AGInventors: Lars Toennes JAKOBSEN, Ljudmil ANASTASOV
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Publication number: 20210364622Abstract: It is suggested to process radar signals including (i) determining a variation of at least one radar parameter provided from at least one radar device; (ii) determining an estimated value of at least one radar parameter from an error compensation vector; and (iii) determining a safety condition based on the variation and the estimated value for the respective radar parameter.Type: ApplicationFiled: May 19, 2021Publication date: November 25, 2021Inventors: Andre Roger, Simon Achatz, Dian Tresna Nugraha, Ljudmil Anastasov, Markus Bichl, Mayeul Jeannin, Farhan Bin Khalid
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Publication number: 20210364596Abstract: It is suggested to process radar signals including: (i) receiving reception signals via at least one antenna of a first receiving circuit; (ii) determining an interim result by processing the reception signals via a frequency transformation; (iii) determining an error compensation vector based on the interim result and an expected characteristic; and (iv) applying the error compensation vector on other reception signals that have been processed via the frequency transformation.Type: ApplicationFiled: May 19, 2021Publication date: November 25, 2021Inventors: Andre Roger, Simon Achatz, Dian Tresna Nugraha, Ljudmil Anastasov, Markus Bichl, Mayeul Jeannin, Maximilian Eschbaumer
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Patent number: 11121810Abstract: A synchronous communication interface includes at least one data channel configured to carry a data signal comprising a plurality of data units; a control channel parallel to the at least one data channel, the control channel configured to carry a control signal for the at least one data channel; and a circuit configured to generate the control signal that includes control information that defines each of the plurality of data units in each data signal and further includes additional information. The circuit is configured to vary a duty cycle of the control signal according to a mapping of the additional information to a plurality of discrete duty cycle states.Type: GrantFiled: September 27, 2019Date of Patent: September 14, 2021Inventors: Ljudmil Anastasov, Markus Bichl
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Publication number: 20200355791Abstract: A radar system may include a set of analog components to perform one or more radio frequency (RF) operations during an active radar phase of the radar system. The radar system may include a set of digital components to perform one or more digital processing operations during at least a digital processing phase of the radar system. The one or more digital processing operations may be performed such that performance of the one or more digital processing operations does not overlap performance of a substantive portion of the one or more RF operations.Type: ApplicationFiled: May 10, 2019Publication date: November 12, 2020Inventors: Witold GORA, Ljudmil ANASTASOV, Thomas LANGSCHWERT, Bejoy MATHEWS
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Publication number: 20200256950Abstract: A method for processing a radar signal includes adjusting a processing clock signal, wherein the processing clock signal determines an operation period of a signal processing circuit, wherein the processing clock signal is determined based on a time window, wherein the size of the time window is determined based on the maximum time available for processing a portion of the radar signal and wherein the end of the time window is determined such that it does not occur during an active transmission portion of the radar system.Type: ApplicationFiled: January 24, 2020Publication date: August 13, 2020Inventors: Markus Bichl, Ljudmil Anastasov, Romain Ygnace
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Publication number: 20200244398Abstract: A synchronous communication interface includes at least one data channel configured to carry a data signal comprising a plurality of data units; a control channel parallel to the at least one data channel, the control channel configured to carry a control signal for the at least one data channel; and a circuit configured to generate the control signal that includes control information that defines each of the plurality of data units in each data signal and further includes additional information. The circuit is configured to vary a duty cycle of the control signal according to a mapping of the additional information to a plurality of discrete duty cycle states.Type: ApplicationFiled: September 27, 2019Publication date: July 30, 2020Applicant: Infineon Technologies AGInventors: Ljudmil ANASTASOV, Markus Bichl
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Patent number: 10191795Abstract: Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.Type: GrantFiled: June 23, 2017Date of Patent: January 29, 2019Assignee: Infineon Technologies AGInventors: Karl Herz, Ljudmil Anastasov, Harald Zweck
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Patent number: 10128783Abstract: A drive circuit includes an internal oscillator and a pre-drive controller coupled to the internal oscillator. The pre-drive controller can have a switch control output configured to be coupled to a switch input. The pre-drive controller can receive switch control data, receive a clock signal, receive a synchronization signal, synchronize the internal oscillator based on the clock signal and the synchronization signal, and generate a pulse modulated switching signal at the switch control output based on the switch control data and the internal oscillator.Type: GrantFiled: May 31, 2016Date of Patent: November 13, 2018Assignee: Infineon Technologies AGInventors: Matthias Bogus, Christian Heiling, Ljudmil Anastasov, Benno Koeppl
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Patent number: 9923750Abstract: A modulator operable to control an oscillator is described. The modulator can include a memory that stores oscillator control values and a bit streaming block. The bit streaming block can generate a bit stream based on the oscillator control values and transmit the bit stream to the oscillator to control an oscillation frequency of the oscillator. The modulator can also include a bit streaming loader (BSL). The BSL can receive one or more of the oscillator control values from the memory, generate one or more corresponding bit values based on the one or more of the oscillator control values, and provide the one or more bit values to the bit streaming block. The bit streaming block can then generate the bit stream based the one or more bit values generated by the BSL.Type: GrantFiled: June 16, 2016Date of Patent: March 20, 2018Assignee: Infineon Technologies AGInventors: Andre Roger, Romain Ygnace, Juergen Schaefer, Matthias Marquardt, Ljudmil Anastasov
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Publication number: 20170366385Abstract: A modulator operable to control an oscillator is described. The modulator can include a memory that stores oscillator control values and a bit streaming block. The bit streaming block can generate a bit stream based on the oscillator control values and transmit the bit stream to the oscillator to control an oscillation frequency of the oscillator. The modulator can also include a bit streaming loader (BSL). The BSL can receive one or more of the oscillator control values from the memory, generate one or more corresponding bit values based on the one or more of the oscillator control values, and provide the one or more bit values to the bit streaming block. The bit streaming block can then generate the bit stream based the one or more bit values generated by the BSL.Type: ApplicationFiled: June 16, 2016Publication date: December 21, 2017Inventors: Andre Roger, Romain Ygnace, Juergen Schaefer, Matthias Marquardt, Ljudmil Anastasov
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Publication number: 20170346419Abstract: A drive circuit includes an internal oscillator and a pre-drive controller coupled to the internal oscillator. The pre-drive controller can have a switch control output configured to be coupled to a switch input. The pre-drive controller can receive switch control data, receive a clock signal, receive a synchronization signal, synchronize the internal oscillator based on the clock signal and the synchronization signal, and generate a pulse modulated switching signal at the switch control output based on the switch control data and the internal oscillator.Type: ApplicationFiled: May 31, 2016Publication date: November 30, 2017Inventors: Matthias Bogus, Christian Heiling, Ljudmil Anastasov, Benno Koeppl
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Publication number: 20170293519Abstract: Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.Type: ApplicationFiled: June 23, 2017Publication date: October 12, 2017Inventors: Karl Herz, Ljudmil Anastasov, Harald Zweck
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Patent number: 9727400Abstract: Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.Type: GrantFiled: October 13, 2015Date of Patent: August 8, 2017Assignee: Infineon Technologies AgInventors: Karl Herz, Ljudmil Anastasov, Harald Zweck
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Patent number: 9479310Abstract: Described herein are implementations relating to a method for an apparatus to communicate with a device. One embodiment includes transmitting a clock signal to the device, receiving from the device, an asynchronous signal, and extracting information from the asynchronous signal based on the clock signal. In one embodiment the clock signal has a periodic elementary pattern. A period of the clock signal, in one embodiment encompasses, more than one clock cycle. Further disclosed are an apparatus to communicate with a device and a system for communication with a device.Type: GrantFiled: August 6, 2013Date of Patent: October 25, 2016Assignee: Infineon Technologies AGInventors: Ljudmil Anastasov, Kim Wee Ng
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Patent number: 9323654Abstract: An apparatus including a memory having an array of blocks addressable using address bits; and a permutation circuit coupled to the memory and configured to permutate the address bits such that during a memory access blocks of data are rearranged virtually.Type: GrantFiled: July 17, 2013Date of Patent: April 26, 2016Assignee: Infineon Technologies AGInventor: Ljudmil Anastasov
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Publication number: 20160041862Abstract: Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or communication channels to a corresponding one of a plurality of timeout timers when corresponding commands are to be transmitted or command acknowledges are received respectively.Type: ApplicationFiled: October 13, 2015Publication date: February 11, 2016Inventors: Karl Herz, Ljudmil Anastasov, Harald Zweck