Patents by Inventor Loc Tu
Loc Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230315330Abstract: A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current operation of the non-volatile storage apparatus to make a second level prediction about defects. In one embodiment, the first level prediction is faster to make and uses less data collection, but is not as reliable, as the second level prediction. While second level prediction is more reliable, it takes more time to perform and requires a more intensive data collection, so it is only used when needed.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Liang Li, Loc Tu, Yinfeng Yu, Xuan Tian
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Patent number: 11756630Abstract: Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.Type: GrantFiled: August 12, 2021Date of Patent: September 12, 2023Assignee: Western Digital Technologies, Inc.Inventors: Liang Li, Qianqian Yu, Jiahui Yuan, Loc Tu
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Patent number: 11687252Abstract: A non-volatile storage apparatus comprises one or more memory die assemblies, each of which includes an inference circuit positioned in the memory die assembly. The inference circuit is configured to use a pre-trained model (received pre-trained from a source external to the non-volatile storage apparatus and stored in a dedicated block in non-volatile memory) with one or more metrics describing current operation of the non-volatile storage apparatus in order to predict a defect in the non-volatile storage apparatus and perform a countermeasure to preserve host data prior to a non-recoverable failure in the non-volatile storage apparatus due to the defect.Type: GrantFiled: October 18, 2021Date of Patent: June 27, 2023Assignee: Western Digital Technologies, Inc.Inventors: Liang Li, Yinfeng Yu, Loc Tu
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Publication number: 20230124035Abstract: A non-volatile storage apparatus comprises one or more memory die assemblies, each of which includes an inference circuit positioned in the memory die assembly. The inference circuit is configured to use a pre-trained model (received pre-trained from a source external to the non-volatile storage apparatus and stored in a dedicated block in non-volatile memory) with one or more metrics describing current operation of the non-volatile storage apparatus in order to predict a defect in the non-volatile storage apparatus and perform a countermeasure to preserve host data prior to a non-recoverable failure in the non-volatile storage apparatus due to the defect.Type: ApplicationFiled: October 18, 2021Publication date: April 20, 2023Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Liang Li, Yinfeng Yu, Loc Tu
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Publication number: 20230048326Abstract: Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Applicant: Western Digital Technologies, Inc.Inventors: Liang Li, Qianqian Yu, Jiahui Yuan, Loc Tu
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Patent number: 11372056Abstract: Techniques and apparatuses are provided for detecting a short circuit between pins of an integrated circuit package. The tested pins can be adjacent or non-adjacent on the package. Various types of short circuits can be detected, including resistive, diode and capacitive short circuits. Additionally, short circuits of a single pin can be tested, including a short circuit to a power supply or to ground. The test circuit includes a current mirror, where the input path has a first path connected to a first pin and a parallel second path connected to a second pin. A comparator is connected to the output path of the current mirror. By controlling the on and off states of transistors in the first and second paths, and evaluating the voltage of the output path, the short circuits can be detected.Type: GrantFiled: May 26, 2020Date of Patent: June 28, 2022Assignee: SanDisk Technologies LLCInventors: Dat Tran, Loc Tu, Kirubakaran Periyannan, Nyi Nyi Thein
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Publication number: 20210373085Abstract: Techniques and apparatuses are provided for detecting a short circuit between pins of an integrated circuit package. The tested pins can be adjacent or non-adjacent on the package. Various types of short circuits can be detected, including resistive, diode and capacitive short circuits. Additionally, short circuits of a single pin can be tested, including a short circuit to a power supply or to ground. The test circuit includes a current mirror, where the input path has a first path connected to a first pin and a parallel second path connected to a second pin. A comparator is connected to the output path of the current mirror. By controlling the on and off states of transistors in the first and second paths, and evaluating the voltage of the output path, the short circuits can be detected.Type: ApplicationFiled: May 26, 2020Publication date: December 2, 2021Applicant: SanDisk Technologies LLCInventors: Dat Tran, Loc Tu, Kirubakaran Periyannan, Nyi Nyi Thein
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Patent number: 11086539Abstract: Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X>1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.Type: GrantFiled: October 21, 2019Date of Patent: August 10, 2021Assignee: SanDisk Technologies LLCInventors: Dat Tran, Loc Tu, Kirubakaran Periyannan
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Publication number: 20210117086Abstract: Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X>1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.Type: ApplicationFiled: October 21, 2019Publication date: April 22, 2021Applicant: SanDisk Technologies LLCInventors: Dat Tran, Loc Tu, Kirubakaran Periyannan
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Patent number: 10984883Abstract: A memory management method includes identifying memory segments of a memory device. The method also includes identifying, for each memory segment, a number of faulty columns and determining a total number of faulty columns for the memory device. The method also includes, in response to a determination that the total number of faulty columns is greater than a threshold, identifying a memory segment having a highest number of faulty columns. The method also includes disabling the memory segment. Another method includes identifying, for each memory segment, a number of faulty memory blocks and determining a total number of faulty memory blocks. The method also includes, in response to a determination that the total number of faulty memory blocks is greater than a threshold, identifying a memory segment having a highest number of faulty memory blocks. The method also includes disabling the memory segment.Type: GrantFiled: December 27, 2019Date of Patent: April 20, 2021Assignee: SanDiskTechnologies LLCInventors: Sowjanya Tungala, Sini Balakrishnan, Sowjanya Sunkavelli, Sridhar Yadala, Dat Tran, Loc Tu, Kirubakaran Periyannan
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Patent number: 9218895Abstract: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).Type: GrantFiled: August 5, 2014Date of Patent: December 22, 2015Assignee: SanDisk Technologies Inc.Inventors: Charles Moana Hook, Loc Tu, Nyi Nyi Thein, James Floyd Cardosa, Ian Arthur Myers
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Publication number: 20140351653Abstract: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).Type: ApplicationFiled: August 5, 2014Publication date: November 27, 2014Inventors: Charles Moana Hook, Loc Tu, Nyi Nyi Thein, James Floyd Cardosa, Ian Arthur Myers
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Patent number: 8826086Abstract: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).Type: GrantFiled: February 7, 2011Date of Patent: September 2, 2014Assignee: SanDisk Technologies Inc.Inventors: Charles Moana Hook, Loc Tu, Nyi Nyi Thein, James Floyd Cardosa, Ian Arthur Myers
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Patent number: 8446772Abstract: Techniques are disclosed herein for automatically self-disabling a memory die in the event that a programmable element on the memory die for indicating whether the memory die is defective cannot be trusted. Memory die are provided with chip enable circuitry to allow particular memory die to be disabled. If the programmable element can be trusted, the state of the programmable element is provided to the chip enable circuitry to enable/disable the memory die based on the state. However, if the programmable element cannot be trusted, then the chip enable circuitry may automatically disable the memory die. This provides a greater yield for multi-chip memory packages because packages having memory die with a programmable element that cannot be trusted can still be used.Type: GrantFiled: August 4, 2011Date of Patent: May 21, 2013Assignee: SanDisk Technologies Inc.Inventors: Loc Tu, Charles Moana Hook, Nyi Nyi Thein
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Publication number: 20130033935Abstract: Techniques are disclosed herein for automatically self-disabling a memory die in the event that a programmable element on the memory die for indicating whether the memory die is defective cannot be trusted. Memory die are provided with chip enable circuitry to allow particular memory die to be disabled. If the programmable element can be trusted, the state of the programmable element is provided to the chip enable circuitry to enable/disable the memory die based on the state. However, if the programmable element cannot be trusted, then the chip enable circuitry may automatically disable the memory die. This provides a greater yield for multi-chip memory packages because packages having memory die with a programmable element that cannot be trusted can still be used.Type: ApplicationFiled: August 4, 2011Publication date: February 7, 2013Inventors: Loc Tu, Charles Moana Hook, Nyi Nyi Thein
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Publication number: 20120201091Abstract: A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).Type: ApplicationFiled: February 7, 2011Publication date: August 9, 2012Inventors: Charles Moana Hook, Loc Tu, Nyi Nyi Thein, James Floyd Cardosa, Ian Arthur Myers
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Patent number: 8018769Abstract: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be used to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.Type: GrantFiled: October 5, 2009Date of Patent: September 13, 2011Assignee: Sandisk Technologies Inc.Inventors: Loc Tu, Charles Moana Hook, Yan Li
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Patent number: 7715255Abstract: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be readdressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.Type: GrantFiled: June 14, 2007Date of Patent: May 11, 2010Assignee: SanDisk CorporationInventors: Loc Tu, Jian Chen, Alex Mak, Tien-Chien Kuo, Long Pham
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Publication number: 20100020614Abstract: In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be used to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.Type: ApplicationFiled: October 5, 2009Publication date: January 28, 2010Inventors: LOC TU, CHARLES MOANA HOOK, YAN LI
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Patent number: 7606077Abstract: High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.Type: GrantFiled: September 12, 2006Date of Patent: October 20, 2009Assignee: SanDisk CorporationInventors: Yan Li, Loc Tu, Charles Moana Hook