Abstract: The invention relates to an explosive mass drop test device. Specifically, the present invention relates to a method of designing an explosive block drop test device to serve the explosion test process and meet the requirements for ensuring safety during the test. The present invention gives an example of a test device for dropping explosive masses in the range 50-300 kg. In addition, the structure is designed to be simple, easy to integrate and disassemble with the explosive block, the manipulation of dropped objects is simplified. The product of the present invention can be used to test the safety of explosive blocks.

Abstract: A method of packaging the silicon photonics wafer for fabricating custom optical-electrical modules includes fabricating a wafer with multiple dies of silicon photonics circuits based on custom design and conducting electrical and optical tests of the silicon photonics circuits in wafer level. The method further includes preparing the wafer for next point of use. Additionally, the method includes performing post-wafer processing on the wafer received at the next point of use. The method further includes conducting post-process electrical tests of the silicon photonics circuits in wafer level. Furthermore, the method includes preparing the wafer with known-good-dies or a known-good-wafer identified for custom use. Moreover, the method includes performing custom process on the know good dies.

Abstract: Determining a target's range profiles is an important issue for coastal surveillance radars because it can give us the knowledge about the target, for example, target's type, target's structure and its length along radial direction. Some modern radars nowaday are equipped with the feature of target's range profile extraction, but the results are not accurate due to limitations in processing algorithms. The invention “system and method of determining target's range profiles for coastal surveillance radars” solves the above problem in the direction of proposing a system of technical solutions and associated algorithm improvements.

Abstract: The patent provides the system and the method of evaluation the centroid range-bearing processing in high resolution coastal surveillance radars to solve the problem of assessing the quality of centroid processing. The provided system includes blocks: Input data block, parameter calculation block, evaluation and export result block; The provided method includes steps: Loading input data, calculating parameters, evaluating and exporting results. The system and method provided in this invention solve the issue of the quality assessment of the radar system according to the battle-technical specification at the target centroid level.

Abstract: Determining a target's range profiles is an important issue for coastal surveillance radars because it can give us the knowledge about the target, for example, target's type, target's structure and its length along radial direction. Some modern radars nowaday are equipped with the feature of target's range profile extraction, but the results are not accurate due to limitations in processing algorithms. The invention “system and method of determining target's range profiles for coastal surveillance radars” solves the above problem in the direction of proposing a system of technical solutions and associated algorithm improvements.

Abstract: In one aspect, a method for modeling and analyzing a physical system comprising a plurality of components includes constructing, by a computing device, a model of the plurality of components. The computing device determines that the at least one component in the plurality of components represents a region for which at least a first portion of an associated partial differential equation is linear. The computing device accesses one of a plurality of datasets, the accessed dataset comprising a representation of the first portion of the partial differential equation. The computing device determines that a subset of the plurality of components encapsulates a region for which a second portion of the associated partial differential equation is non-linear. The computing device generates a combined output based on the partial differential equation combining the first portion and the second portion.

Abstract: An embedded MEMS semiconductor substrate is set forth and can be a starting material for subsequent semiconductor device processing. A MEMS device is formed in a semiconductor substrate, including at least one MEMS electrode and a buried silicon dioxide sacrificial layer has been applied for releasing the MEMS. A planarizing layer is applied over the substrate, MEMS device and MEMS electrode. A polysilicon protection layer is applied over the planarizing layer. A silicon nitride capping layer is applied over the polysilicon protection layer. A polsilicon seed layer is applied over the polysilicon nitride capping layer. The MEMS device is released by removing at least a portion of the buried silicon dioxide sacrificial layer and an epitaxial layer is grown over the polysilicon seed layer to be used for subsequent semiconductor wafer processing.

Abstract: An embedded MEMS semiconductor substrate is set forth and can be a starting material for subsequent semiconductor device processing. A MEMS device is formed in a semiconductor substrate, including at least one MEMS electrode and a buried silicon dioxide sacrificial layer has been applied for releasing the MEMS. A planarizing layer is applied over the substrate, MEMS device and MEMS electrode. A polysilicon protection layer is applied over the planarizing layer. A polysilicon nitride capping layer is applied over the polysilicon protection layer. A polysilicon seed layer is applied over the polysilicon nitride capping layer. The MEMS device is released by removing at least a portion of the buried silicon dioxide sacrificial layer and an epitaxial layer is grown over the polysilicon seed layer to be used for subsequent semiconductor wafer processing.

Abstract: A VLSI contact formation process in which a nitride layer is used to stop a wet oxide etch. An anisotropic plasma etch is used to cut a substantially vertical contact hole through the nitride and underlying layers. Thus, the resulting contact hole has a “Y”-shaped profile.

Abstract: A memory cell for an EEPROM memory is fabricated to provide increased oxide thickness at the edge of the tunnel oxide and under the edges of the polysilicon capacitor plate in order to improve the dielectric integrity of the capacitor structure. In one embodiment using a silicided polysilicon process, the oxide is made thicker at the edge of the tunnel oxide by reoxidizing the silicon at the corner of the polysilicon capacitor plate and the underlying substrate surface by exposing the device to a short duration oxidation step after having deposited a 200 Å to 500 Å thick porous oxide over the device to protect the silicide from excessive exposure to the oxidizing ambient. In another embodiment the tunnel oxide is grown in a window in the gate oxide layer, which is about four times thicker than the tunnel oxide, so that the gate oxide completely surrounds the tunnel oxide, and the polysilicon capacitor plate extends beyond the edge of the tunnel oxide terminating at a point above the gate oxide.

Abstract: A memory cell for an EEPROM memory is fabricated to provide increased oxide thickness at the edge of the tunnel oxide and under the edges of the polysilicon capacitor plate in order to improve the dielectric integrity of the capacitor structure. In one embodiment using a silicided polysilicon process, the oxide is made thicker at the edge of the tunnel oxide by reoxidizing the silicon at the corner of the polysilicon capacitor plate and the underlying substrate surface by exposing the device to a short duration oxidation step after having deposited a 200 Å to 500 Å thick porous oxide over the device to protect the silicide from excessive exposure to the oxidizing ambient. In another embodiment the tunnel oxide is grown in a window in the gate oxide layer, which is about four times thicker than the tunnel oxide, so that the gate oxide completely surrounds the tunnel oxide, and the polysilicon capacitor plate extends beyond the edge of the tunnel oxide terminating at a point above the gate oxide.

Abstract: An ultrasound transmission device for utilizing ultrasound energy ultrasound to treat intravascular conditions, such as stenotic and occluded regions of blood vessels, is provided. The ultrasonic transmission device includes a transmission member connectable to the ultrasound energy source on a one end and a tip on the other end. The tip includes a distal section, a proximal section and an intermediate section. The proximal section has a first diameter larger than the transmission member diameter. The intermediate section includes a decreasing step portion, a narrowed portion, and an increasing step portion.

Abstract: An ultrasonic treatment system and method for utilizing ultrasound to treat intravascular conditions, such as stenotic and occluded regions of blood vessels, are provided. The ultrasonic treatment system includes an ultrasonic probe, having a proximal and distal end. A guide catheter and guidewire may also be provided and the probe can be slidably disposed within the guide catheter's inner lumen. The probe can include a horn at the proximal end, a transmission member with a proximal and a distal end connected to the horn at the transmission member proximal end, and a distal tip connected at the transmission member's distal end. The transmission member may include one or more transmission wires, having proximal and distal ends, connected serially or in parallel.

Abstract: An apparatus and method for loading samples into a gel of an electrophoretic gel system (EGS). The preferred sample loader includes a membrane having a net negative charge, net neutral charge or no charge (preferably nitrocellulose or nylon) which releasably retains the samples such that the samples are actively released when the membrane is inserted into the gel of an EGS. In one preferred embodiment, the sample loader includes a substrate having a plurality of sample loading areas extending therefrom. In an alternative embodiment, the membrane is substantially thick and serves as its own substrate. In another embodiment, sample inhibiting agents such as hydrophobic ink are formed through the membrane to inhibit the diffusion of samples between sample loading areas. Each sample loading area includes an affixed membrane. In use, one or more samples to be subjected to electrophoretic action are applied to the membrane before the membrane is inserted into a previously polymerized gel.

Abstract: A memory cell for an EEPROM memory is fabricated to provide increased oxide thickness at the edge of the tunnel oxide and under the edges of the polysilicon capacitor plate in order to improve the dielectric integrity of the capacitor structure. In one embodiment using a silicided polysilicon process, the oxide is made thicker at the edge of the tunnel oxide by reoxidizing the silicon at the corner of the polysilicon capacitor plate and the underlying substrate surface by exposing the device to a short duration oxidation step after having deposited a 200 .ANG. to 500 .ANG. thick porous oxide over the device to protect the silicide from excessivie exposure to the oxidizing ambient. In another embodiment the tunnel oxide is grown in a window in the gate oxide layer, which is about four times thicker than the tunnel oxide, so that the gate oxide completely surrounds the tunnel oxide, and the polysilicon capacitor plate extends beyond the edge of the tunnel oxide terminating at a point above the gate oxide.

Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

Abstract: A method for self-aligned zero-margin contacts to active and poly-1, using silicon nitride or other dielectric material with low reflectivity and etch selectivity to oxide for an etch stop layer and also for sidewall spacers on the gate.

Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

Abstract: A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers.

Abstract: An embedded MEMS semiconductor substrate is set forth and can be a starting material for subsequent semiconductor device processing. A MEMS device is formed in a semiconductor substrate, including at least one MEMS electrode and a buried silicon dioxide sacrificial layer has been applied for releasing the MEMS. A planarizing layer is applied over the substrate, MEMS device and MEMS electrode. A polysilicon protection layer is applied over the planarizing layer. A silicon nitride capping layer is applied over the polysilicon protection layer. A polsilicon seed layer is applied over the polysilicon nitride capping layer. The MEMS device is released by removing at least a portion of the buried silicon dioxide sacrificial layer and an epitaxial layer is grown over the polysilicon seed layer to be used for subsequent semiconductor wafer processing.