Patents by Inventor Loke-Yip Foo
Loke-Yip Foo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063148Abstract: A device is provided, including a bridge substrate and a redistribution layer on a top surface of the bridge substrate. The bridge substrate may include a plurality of trenches extending vertically into the bridge substrate from a bottom surface of the bridge substrate, wherein each of the plurality of trenches may include a conductive filling; a conductive layer partially surrounding the plurality of trenches and separated from the plurality of trenches by a dielectric layer; a plurality of first contact pads under the bottom surface of the bridge substrate and coupled to the conductive layer; and a plurality of second contact pads under the bottom surface of the bridge substrate and coupled to the conductive fillings of the plurality of trenches.Type: ApplicationFiled: August 17, 2022Publication date: February 22, 2024Inventors: Loke Yip FOO, Teong Guan YEW, Bok Eng CHEAH
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Patent number: 11805602Abstract: A chip assembly may include a package substrate that includes one or more pins. The chip assembly may also include one or more pads. The one or more pads may be electrically coupled to the one or more pins. In addition, the chip assembly may include a board that includes one or more board pads. Further, the chip assembly may include an anisotropic layer. The anisotropic layer may be positioned between the board and the one or more pads and between the board and a portion of the package substrate. In addition, the anisotropic layer may mechanically couple the board to the one or more pads and to the portion of the package substrate. Further, the anisotropic layer may electrically couple the one or more pads to the one or more board pads.Type: GrantFiled: November 5, 2020Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Loke Yip Foo, Choong Kooi Chee, Teong Guan Yew
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Publication number: 20230137035Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.Type: ApplicationFiled: December 27, 2022Publication date: May 4, 2023Inventors: Loke Yip FOO, Choong Kooi CHEE
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Publication number: 20230119525Abstract: The present disclosure is directed generally to semiconductor packages, semiconductor package substrates, and methods for making them, which include packages substrates with embedded passive devices positioned between plated through hole vias configured for an improved power delivery network.Type: ApplicationFiled: October 18, 2021Publication date: April 20, 2023Inventors: Loke Yip FOO, Teong Guan YEW, Bok Eng CHEAH
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Patent number: 11562959Abstract: A dual-sided embedded multi-die interconnect bridge provides power and source conduits from the bridge bottom at a silicon portion, in short paths to dice on a die side of an integrated-circuit package substrate. Signal traces are in a metallization on the silicon portion of the dual-sided EMIB. Power, ground and signal vias all emanate from the dual-sided embedded multi-die interconnect bridge, with power and ground entering the bridge from central regions of the silicon portion.Type: GrantFiled: June 25, 2020Date of Patent: January 24, 2023Assignee: Intel CorporationInventors: Loke Yip Foo, Teong Guan Yew, Choong Kooi Chee
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Patent number: 11527481Abstract: According to various examples, a device is described. The device may include a package substrate. The device may also include a plurality of semiconductor devices disposed on the package substrate, wherein the plurality of semiconductor devices comprises top surfaces and bottom surfaces. The device may also include a plurality of interconnects coupled to the package substrate, wherein the plurality of interconnects are adjacent to the plurality of semiconductor devices. The device may also include a flyover bridge coupled to the top surfaces of the plurality of semiconductor devices and the plurality of interconnects, wherein the flyover bridge is directly coupled to the package substrate by the plurality of interconnects, and wherein the bottom surfaces of the plurality of semiconductor devices are electrically isolated from the package substrate.Type: GrantFiled: November 6, 2020Date of Patent: December 13, 2022Assignee: INTEL CORPORATIONInventors: Choong Kooi Chee, Bok Eng Cheah, Teong Guan Yew, Jackson Chung Peng Kong, Loke Yip Foo
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Patent number: 11393758Abstract: A semiconductor device and associated methods are disclosed. In one example, dies are interconnected through a bridge in a substrate. A reference voltage stack extends over at least a portion of the interconnect bridge, and a passive component is coupled to the reference voltage stack. In one example, the passive component helps to reduce interference in the power supply to components in the semiconductor device, such as the dies and the interconnect bridge.Type: GrantFiled: June 25, 2019Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Bok Eng Cheah, Jackson Chung Peng Kong, Loke Yip Foo, Wai Ling Lee
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Publication number: 20220077070Abstract: According to various examples, a device is described. The device may include a package substrate. The device may also include a plurality of semiconductor devices disposed on the package substrate, wherein the plurality of semiconductor devices comprises top surfaces and bottom surfaces. The device may also include a plurality of interconnects coupled to the package substrate, wherein the plurality of interconnects are adjacent to the plurality of semiconductor devices. The device may also include a flyover bridge coupled to the top surfaces of the plurality of semiconductor devices and the plurality of interconnects, wherein the flyover bridge is directly coupled to the package substrate by the plurality of interconnects, and wherein the bottom surfaces of the plurality of semiconductor devices are electrically isolated from the package substrate.Type: ApplicationFiled: November 6, 2020Publication date: March 10, 2022Inventors: Choong Kooi CHEE, Bok Eng CHEAH, Teong Guan YEW, Jackson Chung Peng KONG, Loke Yip FOO
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Publication number: 20220078914Abstract: A chip assembly may include a package substrate that includes one or more pins. The chip assembly may also include one or more pads. The one or more pads may be electrically coupled to the one or more pins. In addition, the chip assembly may include a board that includes one or more board pads. Further, the chip assembly may include an anisotropic layer. The anisotropic layer may be positioned between the board and the one or more pads and between the board and a portion of the package substrate. In addition, the anisotropic layer may mechanically couple the board to the one or more pads and to the portion of the package substrate. Further, the anisotropic layer may electrically couple the one or more pads to the one or more board pads.Type: ApplicationFiled: November 5, 2020Publication date: March 10, 2022Inventors: Loke Yip FOO, Choong Kooi CHEE, Teong Guan YEW
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Publication number: 20210391238Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Inventors: Loke Yip Foo, Choong Kooi Chee
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Patent number: 11107751Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.Type: GrantFiled: February 25, 2019Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Loke Yip Foo, Choong Kooi Chee
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Publication number: 20210098375Abstract: A dual-sided embedded multi-die interconnect bridge provides power and source conduits from the bridge bottom at a silicon portion, in short paths to dice on a die side of an integrated-circuit package substrate. Signal traces are in a metallization on the silicon portion of the dual-sided EMIB. Power, ground and signal vias all emanate from the dual-sided embedded multi-die interconnect bridge, with power and ground entering the bridge from central regions of the silicon portion.Type: ApplicationFiled: June 25, 2020Publication date: April 1, 2021Inventors: Loke Yip Foo, Teong Guan Yew, Choong Kooi Chee
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Publication number: 20200083170Abstract: A semiconductor device and associated methods are disclosed. In one example, dies are interconnected through a bridge in a substrate. A reference voltage stack extends over at least a portion of the interconnect bridge, and a passive component is coupled to the reference voltage stack. In one example, the passive component helps to reduce interference in the power supply to components in the semiconductor device, such as the dies and the interconnect bridge.Type: ApplicationFiled: June 25, 2019Publication date: March 12, 2020Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Loke Yip Foo, Wai Ling Lee
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Publication number: 20190304876Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.Type: ApplicationFiled: February 25, 2019Publication date: October 3, 2019Inventors: Loke Yip Foo, Choong Kooi Chee
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Patent number: 9978735Abstract: Devices and methods related to an integrated circuit device are provided. The integrated circuit device includes a mother die and a daughter die, in which the daughter die embedded is in a substrate of the integrated circuit device. Micro bumps of the mother die and the daughter die interface together to form a direct down connection between the mother die and the daughter die.Type: GrantFiled: September 28, 2016Date of Patent: May 22, 2018Assignee: Altera CorporationInventors: Loke Yip Foo, Choong Kooi Chee, Mei See Chin, Wai Ling Lee, Wei Lun Oo
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Publication number: 20180090474Abstract: Devices and methods related to an integrated circuit device are provided. The integrated circuit device includes a mother die and a daughter die, in which the daughter die embedded is in a substrate of the integrated circuit device. Micro bumps of the mother die and the daughter die interface together to form a direct down connection between the mother die and the daughter die.Type: ApplicationFiled: September 28, 2016Publication date: March 29, 2018Inventors: Loke Yip Foo, Choong Kooi Chee, Mei See Chin, Wai Ling Lee, Wei Lun Oo
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Patent number: 9842181Abstract: The present disclosure relates to an innovative method of assigning signals to general-purpose input/output pads of an integrated circuit chip. An inductance matrix for the input/output pads is obtained. A candidate assignment is made of a differential signal to a pair of the input/output pads, and a differential mutual inductance is determined for each open pad location in relation to the pair of input/output pads. Single-ended signals are assigned to open pad locations having the lowest differential mutual inductances. The jitter contribution due to each assigned single-ended signal is computed, and a total jitter is updated. In a first embodiment, said assigning, computing and updating steps are repeated until the total jitter exceeds a total jitter budget. In a second embodiment, said assigning, computing and updating steps are repeated until a number of assigned single-ended signals is equal to a target number. Other embodiments and features are also disclosed.Type: GrantFiled: May 24, 2016Date of Patent: December 12, 2017Assignee: Altera CorporationInventors: Kyung Suk Oh, Yee Huan Yew, Chee Cheong Tan, Mei See Chin, Wai Ling Lee, Loke Yip Foo, Chooi Ian Loh, Hui Lee Teng
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Patent number: 7081772Abstract: A method for reducing the amount of logic needed to perform logic operations in non-reprogrammable logic devices based on preexisting circuit designs is provided. The logic optimization method reduces die size and power consumption while increasing the performance of the logic device.Type: GrantFiled: June 4, 2004Date of Patent: July 25, 2006Assignee: Altera CorporationInventor: Loke-Yip Foo