Patents by Inventor Lokesh M. Gupta

Lokesh M. Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11423158
    Abstract: Dynamic compression with dynamic multi-stage encryption for a data storage system in accordance with the present description includes, in one aspect of the present description, preserves end-to-end encryption between a host and a storage controller while compressing data which was received from the host in encrypted but uncompressed form, using MIPs and other processing resources of the storage controller instead of the host. In one embodiment, the storage controller decrypts encrypted but uncompressed data received from the host to unencrypted data and compresses the unencrypted data to compressed data. The storage controller then encrypts the compressed data to encrypted, compressed data and stores the encrypted, compressed data in a storage device controlled by the storage controller. Other aspects and advantages may be realized, depending upon the particular application.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 23, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Alistair Leask Symon, Micah Robison, Brian Anthony Rinaldi, Lokesh M. Gupta, Mark Elliott Hack
  • Patent number: 11403562
    Abstract: Provided are a computer program product, system, and method for determining sectors of a track to stage into cache by training a machine learning module. A machine learning module that receives as input performance attributes of system components affected by staging tracks from the storage to the cache and outputs a staging strategy comprising one of a plurality of staging strategy indicating at least one of a plurality of sectors of a track to stage into the cache. A margin of error is determined based on a current value of a performance attribute and a threshold of the performance attribute. An adjusted staging strategy is determined based on the margin of error. The machine learning module is retrained with current performance attributes to output the adjusted staging strategy.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: August 2, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 11379427
    Abstract: A method for improving asynchronous data replication between a primary storage system and a secondary storage system is disclosed. In one embodiment, such a method includes monitoring, in a cache of the primary storage system, unmirrored data elements needing to be mirrored, but that have not yet been mirrored, from the primary storage system to the secondary storage system. The method maintains a regular LRU list designating an order in which data elements are demoted from the cache. The method determines whether a data element at an LRU end of the regular LRU list is an unmirrored data element. In the event the data element at the LRU end of the regular LRU list is an unmirrored data element, the method moves the data element to a transfer-pending LRU list dedicated to unmirrored data elements in the cache. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: July 5, 2022
    Assignee: International Business Machines Corporation
    Inventors: Gail Spear, Lokesh M. Gupta, Kyler A. Anderson, David B. Schreiber, Kevin J. Ash
  • Patent number: 11379382
    Abstract: A method for demoting a selected storage element from a cache memory includes storing favored and non-favored storage elements within a higher performance portion and lower performance portion of the cache memory. The favored storage elements are retained in the cache memory longer than the non-favored storage elements. The method maintains a first favored LRU list and a first non-favored LRU list, associated with the favored and non-favored storage elements stored within the higher performance portion of the cache. The method selects a favored or non-favored storage element to be demoted from the higher performance portion of the cache memory according to life expectancy and residency of the oldest favored and non-favored storage elements in the first LRU lists. The method demotes the selected from the higher performance portion of the cache to the lower performance portion of the cache, or to the data storage devices, according to a cache demotion policy.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: July 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Beth A. Peterson, Matthew G. Borlick
  • Patent number: 11379329
    Abstract: A first server of a storage controller is configured to communicate with a host via a first bus interface, and a second server of the storage controller is configured to communicate with the host via a second bus interface. Data is written from the host via the first bus interface to a cache of the first server and via the second bus interface to a non-volatile storage of the second server. The data stored in the cache of the first server is periodically compared to the data stored in the non-volatile storage of the second server.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: July 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos
  • Patent number: 11372761
    Abstract: A method for dynamically adjusting cache memory partition sizes within a storage system includes computing a read hit ratio for data accessed in each cache partition and an average read hit ratio for all the cache partitions over a time interval. The cache memory includes a higher performance portion (DRAM) and lower performance portion (SCM). The method increases or decreases the partition size for each cache partition by comparing the read hit ratio for the partition to the average read hit ratio for all the partitions. Each cache partition includes maximum and minimum partition sizes, and read hit and read access counters. The SCM portion of the cache memory includes cache partitions reserved for storing data of a specific type, or data used for a specific purpose or with a specific software application. A corresponding storage controller and computer program product are also disclosed.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: June 28, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew G. Borlick
  • Patent number: 11372764
    Abstract: A method for demoting data from a cache comprising heterogeneous memory types is disclosed. The method maintains for a data element in the cache, a write access count that is incremented each time the data element is updated in the cache. The cache includes a higher performance portion and a lower performance portion. The method also maintains, for the data element, a read access count that is incremented each time a data element is read in the cache. The method removes the data element from the higher performance portion of the cache in accordance with a cache demotion algorithm. If the write access count is below a first threshold and the read access count is above a second threshold, the method places the data element in the lower performance portion. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 28, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash, Kyler A. Anderson
  • Patent number: 11372778
    Abstract: A method for demoting a selected storage element from a cache memory includes storing favored and non-favored storage elements within a higher performance portion and lower performance portion of the cache memory. The method maintains a plurality of favored LRU lists and a non-favored LRU list for the higher and lower performance portions of the cache memory. Each favored LRU list contains entries associated with the favored storage elements that have the same unique residency multiplier. The non-favored LRU list includes entries associated with the non-favored storage elements. The method demotes a selected favored or non-favored storage element from the higher and lower performance portions of the cache memory according to a cache demotion policy that provides a preference to favored storage elements over non-favored storage elements based on a computed cache life expectancy, residency time, and the unique residency multiplier.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: June 28, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Beth A. Peterson, Matthew G. Borlick
  • Publication number: 20220188235
    Abstract: A method for dynamically adjusting cache memory partition sizes within a storage system includes computing a read hit ratio for data accessed in each cache partition and an average read hit ratio for all the cache partitions over a time interval. The cache memory includes a higher performance portion (DRAM) and lower performance portion (SCM). The method increases or decreases the partition size for each cache partition by comparing the read hit ratio for the partition to the average read hit ratio for all the partitions. Each cache partition includes maximum and minimum partition sizes, and read hit and read access counters. The SCM portion of the cache memory includes cache partitions reserved for storing data of a specific type, or data used for a specific purpose or with a specific software application. A corresponding storage controller and computer program product are also disclosed.
    Type: Application
    Filed: December 11, 2020
    Publication date: June 16, 2022
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew G. Borlick
  • Publication number: 20220179801
    Abstract: A method for demoting a selected storage element from a cache memory includes storing favored and non-favored storage elements within a higher performance portion and lower performance portion of the cache memory. The favored storage elements are retained in the cache memory longer than the non-favored storage elements. The method maintains a first favored LRU list and a first non-favored LRU list, associated with the favored and non-favored storage elements stored within the higher performance portion of the cache. The method selects a favored or non-favored storage element to be demoted from the higher performance portion of the cache memory according to life expectancy and residency of the oldest favored and non-favored storage elements in the first LRU lists. The method demotes the selected from the higher performance portion of the cache to the lower performance portion of the cache, or to the data storage devices, according to a cache demotion policy.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 9, 2022
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Beth A. Peterson, Matthew G. Borlick
  • Publication number: 20220179802
    Abstract: A method for demoting a selected storage element from a cache memory includes storing favored and non-favored storage elements within a higher performance portion and lower performance portion of the cache memory. The method maintains a plurality of favored LRU lists and a non-favored LRU list for the higher and lower performance portions of the cache memory. Each favored LRU list contains entries associated with the favored storage elements that have the same unique residency multiplier. The non-favored LRU list includes entries associated with the non-favored storage elements. The method demotes a selected favored or non-favored storage element from the higher and lower performance portions of the cache memory according to a cache demotion policy that provides a preference to favored storage elements over non-favored storage elements based on a computed cache life expectancy, residency time, and the unique residency multiplier.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 9, 2022
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Beth A. Peterson, Matthew G. Borlick
  • Patent number: 11354208
    Abstract: A first non-volatile dual in-line memory module (NVDIMM) of a first server and a second NVDIMM of a second server are armed during initial program load in a dual-server based storage system to configure the first NVDIMM and the second NVDIMM to retain data on power loss. Prior to initiating a safe data commit scan to destage modified data from the first server to a secondary storage, a determination is made as to whether the first NVDIMM is armed. In response to determining that the first NVDIMM is not armed, a failover is initiated to the second server.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: June 7, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Sean Patrick Riley, Brian Anthony Rinaldi, Trung N. Nguyen, Lokesh M. Gupta
  • Patent number: 11347426
    Abstract: A computational device receives a command to activate a time lock for a data set. In response to receiving the command to activate the time lock for the data set, a point in time copy of the data set is generated to allow write operations to be performed even if the time lock is activated.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: May 31, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Carol S. Mellgren
  • Patent number: 11341407
    Abstract: Provided are techniques for selecting a disconnect by training a machine learning module. A machine learning module is provided that receives inputs and produces an output. The output produced from the machine learning module based on the inputs for the first I/O operation and an estimated amount of time to acquire resources for a first I/O operation is determined. An actual amount of time to acquire resources for the first I/O operation is determined. The machine learning module is retrained based on the inputs, the output, and the actual amount of time it took to acquire resources for the first I/O operation versus an estimated amount of time to acquire the resources for the first I/O operation. The retrained machine learning module is used to select one of disconnect from a channel, the logical disconnect from the channel, or the physical disconnect from the channel for a second I/O operation.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: May 24, 2022
    Assignee: International Business Machines Corporation
    Inventors: Beth A. Peterson, Lokesh M. Gupta, Matthew R. Craig, Kevin J. Ash
  • Publication number: 20220156166
    Abstract: Provided are a computer program product, system, and method for using a track format code in a cache control block for a track in a cache to process read and write requests to the track in the cache. A track format table associates track format codes with track format metadata. A determination is made as to whether the track format table has track format metadata matching track format metadata of a track staged into the cache. A determination is made as to whether a track format code from the track format table for the track format metadata in the track format table matches the track format metadata of the track staged. A cache control block for the track being added to the cache is generated including the determined track format code when the track format table has the matching track format metadata.
    Type: Application
    Filed: February 2, 2022
    Publication date: May 19, 2022
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos, Beth A. Peterson
  • Patent number: 11334275
    Abstract: Provided are a computer program product, system, and method for reducing a rate at which data is mirrored from a primary server to a secondary server. A determination is made as to whether a processor utilization at a processor managing access to the secondary storage exceeds a utilization threshold. If so, a determination is made as to whether a specified operation at the processor is in progress. A message is sent to the primary server to cause the primary server to reduce a rate at which data is mirrored from the primary server to the secondary server in response to determining that the specified operation is in progress.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 17, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clint A. Hardy, Matthew G. Borlick, Adrian C. Gerhard, Lokesh M. Gupta
  • Patent number: 11321202
    Abstract: Provided are a computer program product, system, and method for recovering storage devices in a storage array having errors. A determination is made to replace a first storage device in a storage array with a second storage device. The storage array is rebuilt by including the second storage device in the storage array and removing the first storage device from the storage array resulting in a rebuilt storage array. The first storage device is recovered from errors that resulted in the determination to replace. Data is copied from the second storage device included in the rebuilt storage array to the first storage device. The recovered first storage device is swapped into the storage array to replace the second storage device in response to copying the data from the second storage device to the first storage device.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: May 3, 2022
    Assignee: International Business Machines Corporation
    Inventors: Brian J. Cagno, John C. Elliott, Matthew G. Borlick, Will A. Wright, Lokesh M. Gupta
  • Patent number: 11321123
    Abstract: Provided are a computer program product, system, and method for determining an optimum number of threads to make available per core in a multi-core processor complex to execute tasks. A determination is made of a first processing measurement based on threads executing on the cores of the processor chip, wherein each core includes circuitry to independently execute a plurality of threads. A determination is made of a number of threads to execute on the cores based on the first processing measurement. A determination is made of a second processing measurement based on the threads executing on the cores of the processor chip. A determination is made of an adjustment to the determined number of threads to execute based on the second processing measurement resulting in an adjusted number of threads. The adjusted number of threads on the cores is utilized to execute instructions.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: May 3, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Anthony Rinaldi, Lokesh M. Gupta, Kevin J. Ash, Matthew J. Kalos, Trung N. Nguyen, Clint A. Hardy, Louis A. Rasor
  • Patent number: 11321133
    Abstract: Provided are a computer program product, system, and method for using a machine learning module to determine an allocation of stage and destage tasks. Storage performance information related to processing of Input/Output (I/O) requests with respect to the storage unit is provided to a machine learning module. The machine learning module receives a computed number of stage tasks and a computed number of destage tasks. A current number of stage tasks allocated to stage tracks from the storage unit to the cache is adjusted based on the computed number of stage tasks. A current number of destage tasks allocated to destage tracks from the cache to the storage unit is adjusted based on the computed number of destage tasks.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: May 3, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 11321252
    Abstract: Provided are a computer program product, system, and method for using at least one machine learning module to select a priority queue from which to process an Input/Output (I/O) request. Input I/O statistics are provided on processing of I/O requests at the queues to at least one machine learning module. Output is received from the at least one machine learning module for each of the queues. The output for each queue indicates a likelihood that selection of an I/O request from the queue will maintain desired response time ratios between the queues. The received output for each of the queues is used to select a queue of the queues. An I/O request from the selected queue is processed.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: May 3, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karl A. Nielsen, Clint A. Hardy, Lokesh M. Gupta, Matthew G. Borlick