Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.

Abstract: A laser preheating control method is applied to a laser preheating control device. When a cutter processes a workpiece along a process path, a laser source of the device is provided to output a laser beam to the workpiece for selectively forming a laser spot on the workpiece surface. And according to a movement direction of the cutter, a laser controller of the device is provided to form the laser spot only on a preheating region of the workpiece, where in front of the cutter in the process path, for preheating the workpiece in the preheating region. As a result, the laser spot will not repeatedly heat the workpiece behind the cutter in the process path, and the qualitative change of the workpiece caused by repeating heating is preventable.

Abstract: An electronic device and an equalizer adjustment method thereof are disclosed. The method comprises the steps of: storing a list of age gain values, the list of age gain values comprising a plurality of age segments, respectively increasing from the first age segment to the Nth age segment, each of the age segments comprising a group correcting parameters, the group correcting parameters including a plurality of compensation gain values respectively corresponding to a plurality of target frequency, and the compensation gain values in the same target frequency are increased as N increases; obtaining an age data of an user; obtaining the target age segment, wherein the target age segment is one of the age segments; obtaining the group correction parameter corresponding to the target age segment; and adjusting a gain value setting of the equalizer to sound at different frequencies according to the group correction parameter.

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

Abstract: A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.

Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.

Abstract: A memory chip comprises a first memory controller, a first data storage zone, a security unit and an address configuration unit. The first data storage zone is coupled to the first memory controller, and represented by a first physical address range. The security unit is coupled to the first memory controller. The address configuration unit is coupled to the first memory controller. The memory chip is configured to be coupled between a host controller and another memory chip. The another memory chip comprises a second data storage zone represented by a second physical address range. The address configuration unit records one or more relationships of a logical address range corresponding to the first physical address range and the second physical address range. The security unit is configured to encrypt and decrypt data in the first data storage zone and the second data storage zone.

Abstract: A memory device comprises a memory array with I/O path and security circuitry coupled to the I/O path of the memory array. The memory device comprises control circuitry, responsive to configuration data, to invoke the security circuitry. The memory device comprises a configuration store, storing the configuration data accessible by the control circuitry to specify location and size of a security memory region in the memory array. Responsive to an external command and the configuration data, the control circuitry can be configured to invoke the security circuitry on an operation specified in the external command in response to accesses into the security memory region, or to not invoke the security circuitry in response to accesses to outside the security memory region.

Abstract: A balancing transporter is provided to mitigate occurrence of undesired sudden turning and falling of a user by virtue of various mechanisms that control the source/cause of mistakes and implement post-mistake remedies. Two adjusting members are operated by the user for turning control in a manner that interference between operations on the adjusting members and on handles is prevented. Maximum allowance of difference between wheel speeds is introduced to prevent sudden turns due to inappropriate operation. A rotational interlock unit mechanically enables the adjusting members to rotate in opposite directions to prevent sudden turns. Shock absorption and balance compensation mechanisms are introduced to keep the balancing transporter from tilting.

Abstract: A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port.

Abstract: A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.

Abstract: A system and method use a physical unclonable function in a PUF circuit on an integrated circuit to generate a security key, and stabilize the security key by storage in a set of nonvolatile memory cells. The stabilized security key is moved from the set of nonvolatile memory cells to a cache memory, and utilized as stored in the cache memory in a security protocol. Also, data transfer from the PUF circuit to the set of nonvolatile memory cells can be disabled after using the PUF circuit to produce the security key, at a safe time, such as after the security key has been moved from the set of nonvolatile memory cells to the cache memory.

Abstract: A system including a host and a guest device, where the guest device can be implemented on a single packaged integrated circuit or a multichip circuit and have logic to use a physical unclonable function to produce a security key. The device can include logic on the guest to provide the PUF key to the host in a secure manner. The physical unclonable function can use entropy derived from non-volatile memory cells to produce the initial key. Logic is described to disable changes to PUF data, and thereby freeze the key after it is stored in the set.

Abstract: A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

Abstract: The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.

Abstract: A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.

Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

Abstract: A biosensor may provide a magnetoresistive (MR) film comprising a nonmagnetic layer may be sandwiched between the two ferromagnetic layers. The MR film may be positioned on a substrate, where the edges of the MR film are in contact with leads. Additionally, the leads may be in contact with pads. The sensors may provide quasi-digital readout that enable greatly enhanced sensitivity. In some embodiments, biosensors may be arranged as array of sensors. The array of sensors may be arranged as a symmetric or asymmetric N1×N2 array, where N1 and N2 are integers, N1 represents the number of sensors linked together in series, and N2 represents the number of sensor sets in parallel, where each sensor set may comprise one or more sensors. Further, the array of sensors may be coupled to a voltmeter, which may be a single voltmeter in some cases that allows the sensors to all be probed simultaneously.

Abstract: A memory device includes a memory including first and second pages in first and second banks, respectively, an address decoder mapping command addresses to physical addresses. The memory device further includes circuitry configured to maintain a status indicating a most recently written page, decode received command sequences including command addresses and implementing an operation including (i) responsive to receiving a command sequence including a read command address that is pre-configured for reading data, causing the address decoder to map the read command address to one of the first and second pages selected according to the status, and (ii) responsive to receiving a second command sequence including a write command address that is pre-configured for writing data, causing the address decoder to map the write command address to one of the first and second pages selected according to the status.

Abstract: A sound adjustment method applied to a sound adjustment system is disclosed. The sound adjustment system includes a sound receiving module, a sound identification module, a sound frequency conversion module and a sound equalizer. The sound adjustment method includes the steps of: receiving a sound signal via the sound receiving module; identifying the sound signal via the sound identification module to determine a type of the sound signal; if the sound signal is a voice signal, executing a frequency conversion of the voice signal via the sound frequency conversion module such that the voice signal becomes a frequency-converted voice signal; if the sound signal is a non-voice signal, adjusting the non-voice signal via the sound equalizer such that the non-voice signal becomes an equalizer-adjusted sound signal.