Patents by Inventor Long Hinh
Long Hinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11810616Abstract: A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N×analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.Type: GrantFiled: May 19, 2022Date of Patent: November 7, 2023Assignee: Infineon Technologies LLCInventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta, Ravindra Kapre
-
Publication number: 20220359006Abstract: A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N×analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.Type: ApplicationFiled: May 19, 2022Publication date: November 10, 2022Applicant: Infineon Technologies LLCInventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta, Ravindra Kapre
-
Publication number: 20220284951Abstract: A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.Type: ApplicationFiled: May 23, 2022Publication date: September 8, 2022Applicant: Infineon Technologies LLCInventors: Venkatraman Prabhakar, Krishnaswamy Ramkumar, Vineet Agrawal, Long Hinh, Swatilekha Saha, Santanu Kumar Samanta, Michael Amundson, Ravindra M. Kapre
-
Patent number: 11367481Abstract: A semiconductor inference device that has a non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which each NVM cell comprises a charge trapping transistor configured to store one of N×analog values corresponding to N×levels of its drain current (ID) or threshold voltage (VT) levels, representing N×weight values for multiply accumulate (MAC) operations. The semiconductor inference device also includes digital-to-analog (DAC) function and multiplexor (mux) function configured to generate an analog MAC result based on the digital inputs converted results and the weight values read results, and analog-to-digital (ADC) function configured to convert the analog MAC result of the mux function to a digital value. Other embodiments of the semiconductor inference device and related methods and systems are also disclosed.Type: GrantFiled: May 25, 2021Date of Patent: June 21, 2022Assignee: Infineon Technologies LLCInventors: Venkataraman Prabhakar, Krishnaswamy Ramkumar, Vineet Agrawal, Long Hinh, Swatilekha Saha, Santanu Kumar Samanta, Michael Amundson, Ravindra M. Kapre
-
Patent number: 11355185Abstract: A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N×analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially.Type: GrantFiled: March 24, 2020Date of Patent: June 7, 2022Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta, Ravindra Kapre
-
Publication number: 20210350850Abstract: A semiconductor inference device that has a non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which each NVM cell comprises a charge trapping transistor configured to store one of N×analog values corresponding to N×levels of its drain current (ID) or threshold voltage (VT) levels, representing N×weight values for multiply accumulate (MAC) operations. The semiconductor inference device also includes digital-to-analog (DAC) function and multiplexor (mux) function configured to generate an analog MAC result based on the digital inputs converted results and the weight values read results, and analog-to-digital (ADC) function configured to convert the analog MAC result of the mux function to a digital value. Other embodiments of the semiconductor inference device and related methods and systems are also disclosed.Type: ApplicationFiled: May 25, 2021Publication date: November 11, 2021Applicant: Cypress Semiconductor CorporationInventors: Venkataraman Prabhakar, Krishnaswamy Ramkumar, Vineet Agrawal, Long Hinh, Swatilekha Saha, Santanu Kumar Samanta, Michael Amundson, Ravindra M. Kapre
-
Publication number: 20210158868Abstract: A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.Type: ApplicationFiled: March 24, 2020Publication date: May 27, 2021Applicant: Cypress Semiconductor CorporationInventors: Venkataraman Prabhakar, Krishnaswamy Ramkumar, Vineet Argrawal, Long Hinh, Swatilekha Saha, Santanu Kumar Samanta, Michael Amundson, Ravindra Kapre
-
Publication number: 20210159346Abstract: A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N×analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially.Type: ApplicationFiled: March 24, 2020Publication date: May 27, 2021Applicant: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta, Ravindra Kapre
-
Patent number: 11017851Abstract: A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.Type: GrantFiled: March 24, 2020Date of Patent: May 25, 2021Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Venkataraman Prabhakar, Krishnaswamy Ramkumar, Vineet Agrawal, Long Hinh, Swatilekha Saha, Santanu Kumar Samanta, Michael Amundson, Ravindra Kapre
-
Patent number: 10192622Abstract: A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.Type: GrantFiled: October 12, 2017Date of Patent: January 29, 2019Assignee: Cypress Semiconductor CorporationInventors: Xiaojun Yu, Venkatraman Prabhakar, Igor Kouznetsov, Long Hinh, Bo Jin
-
Publication number: 20180082746Abstract: A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.Type: ApplicationFiled: October 12, 2017Publication date: March 22, 2018Applicant: Cypress Semiconductor CorporationInventors: Xiaojun Yu, Venkatraman Prabhakar, Igor Kouznetsov, Long Hinh, Bo Jin
-
Patent number: 9627073Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.Type: GrantFiled: September 20, 2016Date of Patent: April 18, 2017Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Xiaojun Yu, Venkatraman Prabhakar, Igor G. Kouznetsov, Long Hinh, Bo Jin
-
Publication number: 20170011800Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.Type: ApplicationFiled: September 20, 2016Publication date: January 12, 2017Inventors: Xiaojun Yu, Venkatraman Prabhakar, Igor G. Kouznetsov, Long Hinh, Bo Jin
-
Patent number: 9378821Abstract: Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.Type: GrantFiled: March 8, 2013Date of Patent: June 28, 2016Assignee: Cypress Semiconductor CorporationInventors: Venkatraman Prabhakar, Long Hinh, Kaveh Shakeri, Sarath C. Puthenthermadam
-
Patent number: 8953380Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.Type: GrantFiled: June 26, 2014Date of Patent: February 10, 2015Assignee: Cypress Semiconductor CorporationInventors: Xiaojun Yu, Venkatraman Prabhakar, Igor Kouznetsov, Long Hinh, Bo Jin
-
Publication number: 20140264552Abstract: A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Venkatraman Prabhakar, Kaveh Shakeri, Long Hinh, Sarath C. Puthenthermadam
-
Patent number: 8670278Abstract: Disclosed herein are a method and apparatus for extending the lifetime of a non-volatile trapped-charge memory. A method includes setting limits of a memory sense window between an intrinsic threshold voltage of a non-volatile trapped-charge memory device and one of an end-of-life (EOL) value of a threshold voltage of a programmed state of the memory device and an EOL value of a threshold voltage of an erased state of the memory device. The data state of the memory device is then sensed.Type: GrantFiled: March 27, 2009Date of Patent: March 11, 2014Assignee: Cypress Semiconductor CorporationInventors: Fredrick B. Jenne, Long Hinh