Patents by Inventor Long Hua Lee
Long Hua Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11842936Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.Type: GrantFiled: July 26, 2021Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
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Publication number: 20230253280Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.Type: ApplicationFiled: April 3, 2023Publication date: August 10, 2023Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
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Patent number: 11621205Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.Type: GrantFiled: March 22, 2021Date of Patent: April 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
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Publication number: 20220199465Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.Type: ApplicationFiled: February 21, 2022Publication date: June 23, 2022Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee
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Patent number: 11257715Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.Type: GrantFiled: September 13, 2019Date of Patent: February 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee
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Patent number: 11201097Abstract: In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.Type: GrantFiled: September 13, 2019Date of Patent: December 14, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Yu Huang, Chih-Wei Wu, Li-Chung Kuo, Long Hua Lee, Sung-Hui Huang, Ying-Ching Shih, Pai Yuan Li
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Publication number: 20210358825Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.Type: ApplicationFiled: July 26, 2021Publication date: November 18, 2021Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
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Patent number: 11121050Abstract: In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.Type: GrantFiled: January 12, 2018Date of Patent: September 14, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Yu Huang, Chih-Wei Wu, Li-Chung Kuo, Long Hua Lee, Sung-Hui Huang, Ying-Ching Shih, Pai Yuan Li
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Patent number: 11075133Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.Type: GrantFiled: November 1, 2018Date of Patent: July 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
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Publication number: 20210210400Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
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Patent number: 11024616Abstract: Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.Type: GrantFiled: May 16, 2019Date of Patent: June 1, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Wei Chen, Li-Chung Kuo, Long-Hua Lee, Szu-Wei Lu, Ying-Ching Shih, Kuan-Yu Huang
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Publication number: 20200365571Abstract: Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.Type: ApplicationFiled: May 16, 2019Publication date: November 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Wei Chen, Li-Chung Kuo, Long-Hua Lee, Szu-Wei Lu, Ying-Ching Shih, Kuan-Yu Huang
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Publication number: 20200006178Abstract: In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Kuan-Yu Huang, Chih-Wei Wu, Li-Chung Kuo, Long Hua Lee, Sung-Hui Huang, Ying-Ching Shih, Pai Yuan Li
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Publication number: 20200006181Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.Type: ApplicationFiled: November 1, 2018Publication date: January 2, 2020Inventors: Yu-Wei Chen, Li-Chung Kuo, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee, Kuan-Yu Huang
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Publication number: 20200006136Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee
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Patent number: 10510595Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.Type: GrantFiled: April 30, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee
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Publication number: 20190333811Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.Type: ApplicationFiled: April 30, 2018Publication date: October 31, 2019Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin, Long Hua Lee
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Publication number: 20190006256Abstract: In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.Type: ApplicationFiled: January 12, 2018Publication date: January 3, 2019Inventors: Kuan-Yu Huang, Chih-Wei Wu, Li-Chung Kuo, Long Hua Lee, Sung-Hui Huang, Ying-Ching Shih, Pai Yuan Li
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Patent number: 10157879Abstract: An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface and a second surface opposite the first surface. The substrate has a through substrate via extending from the first surface towards the second surface. The first die is attached to the substrate, and the first die is coupled to the first surface of the substrate. The second die is attached to the substrate, and the second die is coupled to the first surface of the substrate. A first distance is between a first edge of the first die and a first edge of the second die, and the first distance is in a direction parallel to the first surface of the substrate. The first distance is equal to or less than 200 micrometers.Type: GrantFiled: January 9, 2015Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih, Ying-Da Wang, Li-Chung Kuo, Long Hua Lee, Shin-Puu Jeng, Chen-Hua Yu
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Patent number: 9337063Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.Type: GrantFiled: July 3, 2014Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chen, Long Hua Lee, Chun-Hsing Su, Yi-Lin Tsai, Kung-Chen Yeh, Chung Yu Wang, Jui-Pin Hung, Jing-Cheng Lin