Abstract: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

Abstract: In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.

Abstract: In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.

Abstract: In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.

Abstract: In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.

Abstract: In a non-volatile memory, the initiation of program verification is adaptively set so that programming time is decreased. In one approach, non-volatile storage elements are programmed based on a lower page of data to have a voltage threshold (VTH) that falls within a first VTH distribution or a higher, intermediate VTH distribution. Subsequently, the non-volatile storage elements with the first VTH distribution either remain there, or are programmed to a second VTH distribution, based on an upper page of data. The non-volatile storage elements with the intermediate VTH distribution are programmed to third and fourth VTH distributions. The non-volatile storage elements being programmed to the third VTH distribution are specially identified and tracked. Verification of the non-volatile storage elements being programmed to the fourth VTH distribution is initiated after one of the identified non-volatile storage elements transitions to the third VTH distribution from the intermediate VTH distribution.

Abstract: A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed.

Abstract: Techniques of overcoming a degradation of the apparent charge levels stored in one row of memory cells as a result of subsequently programming an adjacent row of memory cells. After storing the data of the subsequently programmed row elsewhere, the charge levels of its cells are driven to common level. The charge levels of the first row of cells then have a uniform influence from the charge levels of the second row, and, as a result, the chance of successfully reading the data stored in the first row is significantly increased.

Abstract: The main use of the laminar device is for fountain displays. When water flows though the surge suppressor assembly and laminar assembly, this device remove all the turbulent in fluid flow, and display an extreme laminar stream of water.