Abstract: An automatic dead zone time optimization system in a primary-side regulation flyback power supply CCM mode, comprising a closed loop formed by a control system, consisting of a single output DAC midpoint sampling module, a digital control module, a current detection module, a dead zone time calculation module and a PWM driving module, and a controlled synchronous rectification primary-side regulation flyback converter. By means of a DAC Sampling mechanism, a primary-side current is sampled to calculate a secondary-side average current, so as to obtain a primary-side average current Imid_p and a secondary-side average current Is(tmid) in the case of CCM; a secondary-side current is input into the dead zone time calculation module to obtain a reasonable dead zone time td; and finally, the PWM driving module is jointly controlled by a primary-side regulation loop and the obtained dead zone time td.

Abstract: A method for improving the conversion efficiency of a CCM mode of a flyback resonant switch power supply, comprising: presetting a threshold value Tset, calculating a time interval Ttap between adjacent zero points during a present conducting time, outputting a switch-off signal at zero points, and comparing the time interval Ttap with the preset threshold value Tset; when Ttap>Tset, he present switch-off time to be less than a switch-off time of a previous cycle, outputting a switch-on signal; when Ttap=0, controlling the present switch-off time to be greater than a switch-off time of the previous cycle, outputting a switch-on signal; and when 0<Ttap<=Tset, controlling the present switch-off time to be the same as the switch-off time of the previous switch cycle, outputting a switch-on signal.

Abstract: A control system for synchronous rectifying transistor of LLC converter, the system comprising a voltage sampling circuit, a high-pass filtering circuit, a PI compensation and effective value detection circuit, and a control system taking a microcontroller (MCU) as a core. When the LLC converter is operating at a high frequency, a drain-source voltage VDS(SR) of the synchronous rectifying transistor delivers, via the sampling circuit, a change signal of the drain-source voltage during turn-off into the high-pass filtering circuit and the PI compensation and effective value detection circuit to obtain an effective value amplification signal of a drain-source voltage oscillation signal caused by parasitic parameters, and the current value is compared with a previously collected value via a control circuit taking a microcontroller (MCU) as a core, so as to change a turning-on time of the synchronous rectifying transistor in the next period.

Abstract: Provided is a dynamic control method that turns off a primary-side switching transistor when an output voltage exceeds an upper limit, and control the switching of a secondary-side synchronous rectification transistor with a fixed cycle and a fixed duty cycle. During the time that the synchronous rectification transistor is turned on, the energy of a load capacitor at the output end is extracted to the primary side, which causes the output voltage to drop rapidly and the overshoot voltage to decrease greatly.

Abstract: A process corner detection circuit based on a self-timing ring oscillator comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The self-timing ring oscillator (2) consists of m two-input Muller C-elements and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing ring oscillator (2). The number of oscillations of the self-timing ring oscillator (2) in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.

Abstract: Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.

Abstract: An online monitoring unit and a control circuit for ultra-wide voltage range applications are disclosed. Compared with a conventional online monitoring unit, present invention eliminates a need to reserve delay units, replaces flip-flops in the conventional online monitoring unit with a latch, and uses a transition detector with fewer transistors than that of a shadow latch in the conventional online monitoring unit, thereby reducing an area and a power consumption of the online monitoring unit significantly and improving an energy efficiency of online monitoring techniques. In addition, in the ultra-wide voltage range applications, a time borrowing property of the latch adopted by the present invention can be utilized to prevent a timing error caused by process-voltage-temperature (PVT) variations, thus enabling a minimization of a timing margin and ensuring a higher power efficiency. The present invention also discloses a control circuit for use with the online monitoring unit.

Abstract: A control method for improving dynamic response of switch power is based on a closed-loop control system comprising a sampling module, a dynamic control module, an error calculation module, a PID module, a mode control module, and a PWM module. The sampling module samples an output voltage Vo, and the dynamic control module compares the output voltage Vo with a set maximum voltage Vomax, a set minimum voltage Vomin, and a reference voltage Vref, so as to determine whether to adopt a dynamic mode. In the dynamic mode, when the output voltage Vo changes greatly, the output voltage Vo is rapidly restored to a stable voltage by inputting large power or small power.

Abstract: Parasitic high-voltage diodes implemented by integration technology in a high-voltage level shift circuit are used for charging a bootstrap capacitor CB, wherein a power supply end of the high voltage level shift circuit is a high-side floating power supply VB, and a reference ground is a floating voltage PGD that is controlled by a bootstrap control circuit. A first parasitic diode DB1 and a second parasitic diode DB2 are provided between the VB and the PGD. The bootstrap control circuit is controlled by a high-side signal and a low-side signal.

Abstract: An online monitoring unit and a control circuit for ultra-wide voltage range applications are disclosed. Compared with a conventional online monitoring unit, the present invention eliminates the need to reserve delay units, replaces flip-flops in the conventional online monitoring unit with a latch, and uses a transition detector with fewer transistors than that of a shadow latch in the conventional online monitoring unit, thereby reducing the area and the power consumption of the online monitoring unit significantly and improving the energy efficiency of online monitoring techniques. In addition, in the ultra-wide voltage range applications, the time borrowing property of the latch adopted by the present invention can be utilized to prevent a timing error caused by PVT variations, thus enabling the minimization of timing margin and ensuring higher power efficiency. The present invention also discloses a control circuit for use with the online monitoring unit.

Abstract: A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.

Abstract: A control method for improving dynamic response of switch power is based on a closed-loop control system comprising a sampling module, a dynamic control module, an error calculation module, a PID module, a mode control module, and a PWM module. The sampling module samples an output voltage Vo, and the dynamic control module compares the output voltage Vo with a set maximum voltage Vomax, a set minimum voltage Vomin, and a reference voltage Vref, so as to determine whether to adopt a dynamic mode. In the dynamic mode, when the output voltage Vo changes greatly, the output voltage Vo is rapidly restored to a stable voltage by inputting large power or small power.

Abstract: A PVTM-based wide voltage range clock stretching circuit is disclosed. The circuit consists of a PVTM circuit module, a phase clock generation module, a clock synchronization selection module and a control module. The PVTM circuit module monitors in real time the delay information of an on-chip delay unit to monitor the operating environment of the circuit, and feeds the delay information back to the control module. Under the control of a clock stretching enable signal and a clock stretching extent signal, the control module selects a target phase clock from the clocks generated by the phase clock generation module in accordance with the feedback from the PVTM, enabling the stretching of system clock within a single cycle in different PVT conditions. Sophisticated gate devices are not required, and the cost of area and power consumption are kept to minimal.

Abstract: A PVTM-based wide voltage range clock stretching circuit is disclosed. The circuit consists of a PVTM circuit module, a phase clock generation module, a clock synchronization selection module and a control module. The PVTM circuit module monitors in real time the delay information of an on-chip delay unit to monitor the operating environment of the circuit, and feeds the delay information back to the control module. Under the control of a clock stretching enable signal and a clock stretching extent signal, the control module selects a target phase clock from the clocks generated by the phase clock generation module in accordance with the feedback from the PVTM, enabling the stretching of system clock within a single cycle in different PVT conditions. Sophisticated gate devices are not required, and the cost of area and power consumption are kept to minimal.

Abstract: A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.

Abstract: A cache structure for use in implementing reconfigurable system configuration information storage, comprises: layered configuration information cache units: for use in caching configuration information that may be used by a certain or several reconfigurable arrays within a period of time; an off-chip memory interface module: for use in establishing communication; a configuration management unit: for use in managing a reconfiguration process of the reconfigurable arrays, in mapping each subtask in an algorithm application to a certain reconfigurable array, thus the reconfigurable array will, on the basis of the mapped subtask, load the corresponding configuration information to complete a function reconfiguration for the reconfigurable array. This increases the utilization efficiency of configuration information caches.

Abstract: A process corner detection circuit based on a self-timing oscillation ring comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The self-timing oscillation ring (2) consists of m two-input Miller units and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing oscillation ring (2). The number of oscillations of the self-timing oscillation ring (2) in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.

Abstract: Disclosed are a pre-decoding analysis-based configuration information cache management system, comprising a streaming media processing module, a configuration information prefetch FIFO module, a configuration information storage unit, and a cache controller module. Also disclosed is a management method for the pre-decoding analysis-based configuration information cache management system. The present invention allows for increased dynamic reconfiguration efficiency of a large-scale coarse-grained reconfigurable system.

Abstract: Disclosed is an error recovery circuit facing a CPU assembly line, comprising: on-chip monitoring circuits (1), an error signal statistics module (2), a voltage frequency control module (3), an error recovery control module (4), an in-situ error recovery module (5) and an upper-layer error recovery module (6), wherein each of the on-chip monitoring circuits (1) is integrated at the end of each stage of assembly lines of the previous N?1 stages of assembly lines of a CPU kernel with an N-stage assembly line structure, so as to monitor the time sequence information about each clock period of an operating circuit, wherein N is a positive integer which is greater than or equal to 3 and less than 20.

Abstract: A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region.