Abstract: A system and method for preventing contention in a shared memory environment. In one embodiment, a first processor reads a traffic controller which is coupled to a shared memory and to a second processor. The first processor writes its identifier into the traffic controller provided that the traffic controller does not already have an identifier corresponding to the second processor stored therein. If the traffic controller does have an identifier corresponding to the second processor stored therein, the first processor periodically reads the traffic controller until the traffic controller does not have an identifier corresponding to the second processor stored therein. Once the traffic controller has the identifier corresponding to the first processor stored therein, the traffic controller allows the first processor to control access to the shared memory.

Abstract: A keyboard controller supports both a first keyboard/mouse interface and a second keyboard/mouse interface. Data is routed between the first keyboard/mouse interface and a first host interface when the first host interface is active. Data is routed between the first keyboard/mouse interface and a first shell when a second host interface is active. The first shell provides compatible connection between the first keyboard/mouse interface and the second host interface. Data is routed between the second keyboard/mouse interface and the second host interface when the second host interface is active. Data is routed between the second keyboard/mouse interface and a second shell when the first host interface is active. The second shell provides compatible connection between the second keyboard/mouse interface and the first host interface.

Abstract: A system for clamping a clock signal line that prevents clock glitching is disclosed. The system is comprised of a plurality of logic gates which generates a signal to clamp the clock signal line only on the occurrence of the clock signal line being low, a clock clamping signal 26 is generated indicating that a peripheral device wants to clamp the clock signal line, and a start condition is detected indicating that the clock signal line may be clamped.

Abstract: An I/O holdoff mechanism is used to compensate for I/O device inputs being fed through a latency introducing bus. A system includes one or more I/O devices connected through a serial bus to a controller device. Each I/O device includes at least one request pin which is connected to a peripheral device. A serializer in the I/O device responds to a voltage transition occurring on any request pin of the I/O device by forwarding, in a packet over the serial bus, an indicator. The indicator indicates a current voltage on the request pin of the I/O device on which the voltage transition occurred. The controller device includes a deserializer and a bus controller. The deserializer receives the first packet and outputs a signal which indicates a current value for the voltage on the indicated request pin. The deserializer includes a busy output which indicates when the deserializer is busy and when the deserializer is idle.

Abstract: Scan code generation for portable personal computers (PCs) using a matrix keyboard operates to produce keyboard output scan codes corresponding to IBM.RTM. compatible PC/AT scan codes. Key numbers are assigned to one or the other of two classes (simple and complex). Two classes of scan code translation tables (simple and complex) are stored in memory, either ROM or internal RAM memory. Whenever a simple key is operated, the simple table is accessed. The complex scan code table is addressed, in accordance with a set of seven edit rules, utilized in conjunction with the state of operation of multiple keys on the keyboard, to determine the appropriate translation. All of the logic needed to generate the necessary scan codes is collapsed into a structured table-driven mechanism.

Abstract: A computing system encodes and emulates requests signals, such as DMA requests or interrupt requests. A first peripheral device is connected to a first request pin of a first input/output (I/O) device. When the first peripheral device asserts a first request signal on the first request pin, a serializer within the first I/O device generates a first packet. The serializer forwards the first packet to a serial out port of the first I/O device. The first packet identifies the type of request and the direction of the edge transition. The serial out port forwards the first packet to a serial in port of a controller device. Upon the serial in port receiving the first packet, an unserializer within the controller device asserts an emulated first request signal, the emulated first request signal being coupled to a first request controller within the controller device.