Abstract: A technique is provided for configuring and controlling complex hardware subsystems that relieves the burden placed on the system programmer and that is, by comparison to present methods, safe and error-free. In accordance with one aspect of the invention, configuration of a hardware subsystem (110) is accomplished by providing in hardware a configuration controller including a controller portion (113) and a storage portion (115) storing configuration parameters. The configuration controller (113) is activated, for example in response to a Configuration/Control ID, and thereupon performs configuration of the hardware subsystem (110), including storing at least one configuration parameter in a register (111) of the hardware subsystem. Typically, the configuration controller hardware (113) and storage (115) are embedded within the hardware subsystem to be configured or controlled.

Abstract: A computer-based software task management system includes an index register configured to store a data register pointer for pointing to a data register. A Task ID register is coupled to the index register and configured to store a Task ID keyed to the index register. A Task ID memory is coupled to the Task ID register and configured to store a flag indicating whether the Task ID is available. A state machine is coupled to the Task ID memory and configured to allocate Task IDs on an available basis using a task ID memory.

Abstract: A computer-based software task management system (100) includes an index register (130) configured to store a data register pointer for pointing to a data register (150). A Task ID register (110) is coupled to the index register and configured to store a Task ID keyed to the index register. A Task ID memory (120) is coupled to the Task ID register and configured to store a flag indicating whether the Task ID is available. A state machine (105) is coupled to the Task ID memory and configured to allocate Task IDs on an available basis using a Task ID memory. Advantages of the invention include the ability to efficiently manage a multithreaded operating system with virtually no additional software overhead.

Abstract: A hardware register content retention system (100) includes a hardware register (110) configured to store register content and a memory (120) capable of storing multiple entries per register coupled to the hardware register, configured to receive a dump of the register content from the hardware register in response to initiation of a task interrupt and to restore the register content to the hardware register in response to termination of the task interrupt. The retention system also includes a controller (130) coupled to the hardware register and the memory, configured to control transfer of the register content between the hardware register and the memory. In one aspect of the invention, the memory is a first-in, first-out (FIFO) queue. The present invention enables more efficient retention of hardware register content than approaches implemented in software. Further, register content may be saved in parallel thereby increasing the speed of register content retention.

Abstract: A technique is provided for configuring and controlling complex hardware subsystems that relieves the burden placed on the system programmer and that is, by comparison to present methods, safe and error-free. In accordance with one aspect of the invention, configuration of a hardware subsystem (110) is accomplished by providing in hardware a configuration controller including a controller portion (113) and a storage portion (115) storing configuration parameters. The configuration controller (113) is activated, for example in response to a Configuration/Control ID, and thereupon performs configuration of the hardware subsystem (110), including storing at least one configuration parameter in a register (111) of the hardware subsystem. Typically, the configuration controller hardware (113) and storage (115) are embedded within the hardware subsystem to be configured or controlled.

Abstract: Among the embodiments of the present invention is a technique that includes executing a first protocol on test bus (40) in accordance with an established test standard to operate a first topology of several test ports (70) and activating to a shadow controller (60) by executing a second protocol on test bus (40). Operation of the test ports (70) is suspended during execution of the second protocol. During activation, the shadow controller (60) can be used to set-up a second topology of one or more of test ports (70) for operation after the test port suspension is discontinued.

Abstract: A method and system that enables real-time peripheral devices to be connected to a computer system utilizing Universal Serial Bus architecture. The present invention empowers the computer system to perform an accurate determination of the moment in time a predetermined event occurred within a real-time peripheral device by utilizing the start of frame pulse transmitted from a USB host controller to peripheral devices connected to it. When a predetermined event occurs within a peripheral device, a first timer within the peripheral device starts incrementing to determine the amount of time that elapses until the next start of frame occurs. Once the next start of frame occurs, the first timer stops incrementing and stores the time before start of frame value. Every start of frame pulse causes a second timer located within the USB host controller to start incrementing.

Abstract: A method and system that enables real-time peripheral devices to be connected to a computer system utilizing Universal Serial Bus architecture. The present invention empowers the computer system to perform an accurate determination of the moment in time a predetermined event occurred within a real-time peripheral device by utilizing the start of frame pulse transmitted from a USB host controller to peripheral devices connected to it. When a predetermined event occurs within a peripheral device, a first timer within the peripheral device starts incrementing to determine the amount of time that elapses until the next start of frame occurs. Once the next start of frame occurs, the first timer stops incrementing and stores the time before start of frame value. Every start of frame pulse causes a second timer located within the USB host controller to start incrementing.

Abstract: The system of the present invention comprises a system for implementing a real time capability in peripheral devices. The system of the present invention functions with a computer system including a processor, a memory, and a video controller, each coupled to a system bus. A USB (universal serial bus) controller is also coupled to the system bus for interfacing peripheral devices on a USB cable to the computer system. A first and second register are included in the USB controller for storing a controller frame number and a controller frame remaining, and a second and third register are included in the peripheral device for storing a device frame number and a device frame remaining. The peripheral device is coupled to the USB controller via a USB cable. A screen reference register is coupled to receive the controller frame number and the controller frame remaining from the USB controller and is coupled to receive a reference signal from a video controller.

Abstract: The present invention relates to a system and method for implementing peripheral device bus mastering via a general purpose list processor. The system is comprised of four main elements: a bus controller, a DMA controller, a list processor, and a device controller. The system operates under two modes of operation. The two modes arise from the two distinct modules: the DMA controller and the list processor. The first mode of operation is a single buffer transfer mode which is directly compatible with a distributed DMA model. Under this mode, distributed DMA registers within the DMA controller are programmed to transfer a single contiguous buffer of data. The second mode of operation is a multiple buffer transfer mode which uses linked lists of buffer transfer descriptors to program the distributed DMA registers within the DMA controller and initiates transfers independent of software.

Abstract: The present invention is a desktop personal computer (PC) system having peripheral device bus mastering. The system has a Direct Memory Access (DMA) controller for transferring data to and from the memory of the desktop PC system. A hardware state machine is used for programming the DMA controller, generating and sending command signals, and receiving completion status after the transfer of data is complete. A bus controller is used for implementing a memory data transfer request from the DMA controller means and said hardware state machine means. A device controller, either a Universal Serial Bus (USB) controller or an Infrared Data Association (IrDA) controller, is used for receiving and responding to the command signals from the hardware state machine means, transferring data to and from the DMA controller means, and generating and returning a completion status to the hardware state machine means after the transfer of data is complete.

Abstract: The present invention is a desktop personal computer (PC) system having peripheral device bus mastering. The system has four main elements: a Direct Memory Access (DMA) controller, a hardware state machine, a bus controller, and a device controller. The device controller may be an IDE hard disk controller which is able to generate long streams of data in an intermittent fashion wherein any single stream of data is targeted to a number of different host memory locations. The device controller may also be an ECP parallel port controller which interfaces with a number of different peripheral devices over a parallel bus wherein each peripheral device appears to the system as a separate and independent data path.

Abstract: The present invention relates to a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the mobile computer system's microcontroller for programming a DMA controller, generating and sending command signals, and receiving completion status after transfer of data is complete. The micro-controller accesses a data buffer descriptor list. The data buffer descriptor list describes each data transfer that the micro-controller initiates, controls, and completes. The Direct Memory Access controller which is programmed by the micro-controller transfers data to and from a memory section of the mobile computer system. A bus controller is used for implementing a memory data transfer request from the DMA controller means and the micro-controller means.

Abstract: The present invention is a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the micro-controller of the mobile computer system to program a DMA controller. The DMA controller transfers data to and from the memory of the mobile computer system. A bus controller which is coupled to both the micro-controller and the DMA controller implements a memory data transfer request from the DMA controller and the micro-controller. A device controller, either a IDE hard disk controller or an ECP parallel port controller, is also coupled to the DMA controller and the micro-controller. The device controller receives and responds to the command signals from the micro-controller by transferring data to and from the DMA controller means and generating a completion signal when the transfer is complete.