Abstract: An electronic device includes a pixel array having a plurality of rows with active imaging pixels, and at least one row with test pixels. Each of the test pixels includes a test voltage generation circuit generating a test voltage, a switching circuit receiving the test voltage and an image pixel output signal and passing the test voltage as output when in a test mode, a comparison circuit receiving the output from the switching circuit and an analog to digital conversion signal and asserting a counter reset signal when the output from the switching circuit and the analog to digital conversion signal are equal in voltage, and a counter beginning counting at a beginning of each test cycle within the test mode, stopping counting upon assertion of the counter reset signal, and outputting its count upon stopping counting. The count is proportional to the test voltage when in the test mode.

Abstract: An electronic device includes a test voltage generation circuit to generate a test voltage as a function of a regulator voltage, and a switching circuit to receive the test voltage and an image pixel output signal, and to pass the test voltage as output when in a test mode. A comparison circuit receives the output from the switching circuit and an analog to digital conversion signal, and asserts a counter reset signal when the output from the switching circuit and the analog to digital conversion signal are equal in voltage. A counter begins counting at a beginning of each test cycle within the test mode, stops counting upon assertion of the counter rest signal, and outputs its count upon stopping counting. The count is proportional to the test voltage when in the test mode.

Abstract: In an embodiment, an image sensor includes: first and second voltage rails; first and second regulators configured to generate first and second regulated voltage at the first and second voltage rails, respectively; and a plurality of pixels coupled to the first and second voltage rails. Each pixel includes: first and second transistor coupled first and second storage capacitor, respectively. A third transistor is coupled between a control terminal of the first transistor and the first or second voltage rails. The third transistor is configured to limit a slew rate of current flowing between the control terminal of the second transistor and the first or second voltage rails to a first slew rate when the image sensor operates in global shutter mode, and to a second slew rate when the image sensor operates in rolling mode, the first slew rate being smaller than the second slew rate.

Abstract: An electronic device includes a voltage divider producing different reference voltages. Dummy pixels each are formed by a transfer gate transistor having a first conduction terminal coupled to a floating diffusion node, a second conduction terminal, and a control node coupled to a first gate signal line, a transmission gate coupled between one of the plurality of taps and the second conduction terminal of the transfer gate transistor, a floating diffusion capacitor coupled between the floating diffusion node and ground, a transistor having a first conduction terminal coupled to the floating diffusion node, a second conduction terminal, and a control terminal coupled to a second gate signal line, and a reset transistor having a first conduction terminal coupled to the upper reference voltage, a second conduction terminal coupled to the second conduction terminal of the transistor, and a control terminal coupled to a reset signal line.

Abstract: An electronic device includes a voltage divider producing different reference voltages. Dummy pixels each are formed by a transfer gate transistor having a first conduction terminal coupled to a floating diffusion node, a second conduction terminal, and a control node coupled to a first gate signal line, a transmission gate coupled between one of the plurality of taps and the second conduction terminal of the transfer gate transistor, a floating diffusion capacitor coupled between the floating diffusion node and ground, a transistor having a first conduction terminal coupled to the floating diffusion node, a second conduction terminal, and a control terminal coupled to a second gate signal line, and a reset transistor having a first conduction terminal coupled to the upper reference voltage, a second conduction terminal coupled to the second conduction terminal of the transistor, and a control terminal coupled to a reset signal line.

Abstract: An electronic device includes an array of image pixels, with the array of image pixels having inputs coupled to control lines and outputs coupled to output lines, and at least one array of dummy pixels, with the at least one array of dummy pixels having inputs coupled to the control lines. Each dummy pixel of the at least one array of dummy pixels is configured to provide a certain output signal in an absence of a fault with at least one of the control lines or of a fault with at least one of the output lines, such that a lack of output of the certain output signal by one or more of the dummy pixels of the at least one array of dummy pixels indicates the fault.

Abstract: An electronic device includes a test voltage generation circuit to generate a test voltage as a function of a regulator voltage, and a switching circuit to receive the test voltage and an image pixel output signal, and to pass the test voltage as output when in a test mode. A comparison circuit receives the output from the switching circuit and an analog to digital conversion signal, and asserts a counter reset signal when the output from the switching circuit and the analog to digital conversion signal are equal in voltage. A counter begins counting at a beginning of each test cycle within the test mode, stops counting upon assertion of the counter rest signal, and outputs its count upon stopping counting. The count is proportional to the test voltage when in the test mode.

Abstract: An electronic device includes an array of image pixels, with the array of image pixels having inputs coupled to control lines and outputs coupled to output lines, and at least one array of dummy pixels, with the at least one array of dummy pixels having inputs coupled to the control lines. Each dummy pixel of the at least one array of dummy pixels is configured to provide a certain output signal in an absence of a fault with at least one of the control lines or of a fault with at least one of the output lines, such that a lack of output of the certain output signal by one or more of the dummy pixels of the at least one array of dummy pixels indicates the fault.

Abstract: The present disclosure provides a method for detecting flicker DC voltage offset. The method includes receiving an output signal of an image sensor, the output signal comprising a reference signal and an image signal, and generating a combined signal by combining the image signal with a peak flicker DC voltage signal during a first time period. The method also includes performing an auto zero function in an auto zeroing comparator during the first time period between the reference signal and the combined signal and comparing the reference signal and the image signal with the auto zeroing comparator during a second time period subsequent to the first time period. The method further include storing a first charge corresponding to the image signal during a second time period and storing a second charge corresponding to a current peak flicker DC voltage signal.

Abstract: The present disclosure provides a method for detecting flicker DC voltage offset. The method includes receiving an output signal of an image sensor, the output signal comprising a reference signal and an image signal, and generating a combined signal by combining the image signal with a peak flicker DC voltage signal during a first time period. The method also includes performing an auto zero function in an auto zeroing comparator during the first time period between the reference signal and the combined signal and comparing the reference signal and the image signal with the auto zeroing comparator during a second time period subsequent to the first time period. The method further include storing a first charge corresponding to the image signal during a second time period and storing a second charge corresponding to a current peak flicker DC voltage signal.