Patents by Inventor Loon Kwang Tan
Loon Kwang Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230253365Abstract: Circuit boards, LED lighting systems and methods of manufacture are described. A circuit board includes a ceramic carrier and a body on the ceramic carrier. The body includes dielectric layers and slots formed completely through a thickness of the dielectric layers. The slots are filled with a dielectric material. A conductive pad is provided on a surface of each of the slots opposite the ceramic carrier.Type: ApplicationFiled: April 19, 2023Publication date: August 10, 2023Applicant: LUMILEDS LLCInventors: Loon-Kwang TAN, Tze Yang HIN
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Patent number: 11664347Abstract: Circuit boards, LED lighting systems and methods of manufacture are described. A circuit board includes a ceramic carrier and a body on the ceramic carrier. The body includes dielectric layers and slots formed completely through a thickness of the dielectric layers. The slots are filled with a dielectric material. A conductive pad is provided on a surface of each of the slots opposite the ceramic carrier.Type: GrantFiled: March 4, 2020Date of Patent: May 30, 2023Assignee: LUMILEDS LLCInventors: Loon-Kwang Tan, Tze Yang Hin
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Publication number: 20210210463Abstract: Circuit boards, LED lighting systems and methods of manufacture are described. A circuit board includes a ceramic carrier and a body on the ceramic carrier. The body includes dielectric layers and slots formed completely through a thickness of the dielectric layers. The slots are filled with a dielectric material. A conductive pad is provided on a surface of each of the slots opposite the ceramic carrier.Type: ApplicationFiled: March 4, 2020Publication date: July 8, 2021Applicant: LUMILEDS LLCInventors: Loon-Kwang TAN, Tze Yang HIN
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Patent number: 9748197Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.Type: GrantFiled: June 24, 2016Date of Patent: August 29, 2017Assignee: Altera CorporationInventors: Loon Kwang Tan, Yuanlin Xie, Ping Chet Tan
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Publication number: 20160307868Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Loon Kwang Tan, Yuanlin Xie, Ping Chet Tan
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Patent number: 9425174Abstract: An integrated circuit package may include an integrated circuit die and a package substrate having a conductive pad. A conductive pillar is formed on a front surface of the integrated circuit die and directly contacts the conductive pad. Prior to contacting the conductive pad directly, the conductive pillar may be positioned adjacent to the conductive pad such that it is aligned to the conductive pad. The integrated circuit package further includes an interconnect structure that is formed in the package substrate. The interconnect structure may include conductive traces that are electrically connected to the conductive pad and the conductive pillar. An additional integrated circuit die may be mounted on the package substrate. The additional integrated circuit die may couple to the integrated circuit die through the interconnect structure.Type: GrantFiled: November 18, 2014Date of Patent: August 23, 2016Assignee: Altera CorporationInventors: Tze Yang Hin, Loon Kwang Tan, Chew Ching Lim
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Patent number: 9401287Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.Type: GrantFiled: February 7, 2014Date of Patent: July 26, 2016Assignee: Altera CorporationInventors: Loon Kwang Tan, Yuanlin Xie, Ping Chet Tan
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Patent number: 9337240Abstract: A lead frame for an integrated circuit (IC) package is disclosed. The lead frame includes a center region and a plurality of lead fingers surrounding the center region. The plurality of lead fingers that surrounds the center region defines a periphery region around the center region. A portion of the plurality of lead fingers extends from the center region to hold the center region in place. Tie bars that are typically used to hold the center region in place may not be included in the lead frame.Type: GrantFiled: June 18, 2010Date of Patent: May 10, 2016Assignee: Altera CorporationInventors: Guan Khai Lee, Loon Kwang Tan, Ping Chet Tan, Pheak Ti Teh
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Publication number: 20150228506Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.Type: ApplicationFiled: February 7, 2014Publication date: August 13, 2015Applicant: Altera CorporationInventors: Loon Kwang Tan, Yuanlin Xie, Ping Chet Tan
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Patent number: 8541263Abstract: In an exemplary embodiment, a method takes as an input a package substrate on which multiple capacitors have been mounted in a ring as part of a design to effectuate on-package decoupling. The method involves plasma cleaning the package substrate and the capacitors to remove organic contaminants. The method then involves applying a thermoset plastic to encase the capacitors on the package substrate. In one embodiment, a heated metal mold is utilized and the thermoset plastic is placed therein. The method includes opening the metal mold and curing the molded thermoset plastic by baking the molded thermoset plastic at an elevated temperature.Type: GrantFiled: August 22, 2008Date of Patent: September 24, 2013Assignee: Altera CorporationInventors: Teik Tiong Toong, Loon Kwang Tan
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Patent number: 8525326Abstract: An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.Type: GrantFiled: July 20, 2011Date of Patent: September 3, 2013Assignee: Altera CorporationInventors: Teik Tiong Toong, Loon Kwang Tan
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Publication number: 20110272785Abstract: An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.Type: ApplicationFiled: July 20, 2011Publication date: November 10, 2011Inventors: Teik Tiong Toong, Loon Kwang Tan
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Patent number: 7989942Abstract: An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.Type: GrantFiled: January 20, 2009Date of Patent: August 2, 2011Assignee: Altera CorporationInventors: Teik Tiong Toong, Loon Kwang Tan
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Publication number: 20100181644Abstract: An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.Type: ApplicationFiled: January 20, 2009Publication date: July 22, 2010Inventors: Teik Tiong Toong, Loon Kwang Tan