Abstract: An apparatus is described that has processing circuitry for performing operations, and a communication path employed by the processing circuitry to access a first memory. Switch circuitry, when activated, is connected to the communication path. The processing circuitry issues access commands specifying addresses to be accessed, where each address is mapped to location in a memory system in accordance with a system address map. The memory system comprises at least the first memory and a second memory. When in a particular mode, the processing circuitry performs operations that require access to only a subset of the locations provided in the first memory. The switch circuitry is arranged, whilst the processing circuitry is in the particular mode, to be activated in order to intercept the access commands issued over the communication path that specify addresses mapped by the system address map to locations within the subset of locations.

Abstract: An apparatus is described that has processing circuitry for performing operations, and a communication path employed by the processing circuitry to access a first memory. Switch circuitry, when activated, is connected to the communication path. The processing circuitry issues access commands specifying addresses to be accessed, where each address is mapped to location in a memory system in accordance with a system address map. The memory system comprises at least the first memory and a second memory. When in a particular mode, the processing circuitry performs operations that require access to only a subset of the locations provided in the first memory. The switch circuitry is arranged, whilst the processing circuitry is in the particular mode, to be activated in order to intercept the access commands issued over the communication path that specify addresses mapped by the system address map to locations within the subset of locations.

Abstract: The invention relates to a device to be used with a thread scheduling method, and to a thread scheduling method comprising the steps of performing a scheduling for threads to be executed by a multithreaded (MT) processor (11), characterized in that the scheduling is performed as a function of a variable (idle) representing the processor idle time.

Abstract: The invention relates to a device to be used with a scheduling method, and to a scheduling method, in particular a context scheduling method, comprising the steps of performing a scheduling for threads to be executed by a multithreaded processor, wherein the scheduling is performed as a function of index variables assigned to the threads. That thread whose index variable has the highest, or—in an alternative—the lowest value may be selected as the respective thread to be executed by the processor.

Abstract: An arrangement and a method for processing data of multiprotocol data packets comprises at least one multiplexer connected to input ports; at least one first programmable data processing unit configured to provide header words and into payload words; a buffer management unit configured to generate localization data which specifies a corresponding memory area of the payload memory; a descriptor generator unit for generating data packet descriptors; a RISC processor configured to generate, in dependence on the data packet descriptors, header data for transmit data packets and payload processing instructions for processing data of the data packet payload words, stored in the payload memory, of the associated received data packet; and at least one second programmable data processing unit configured to process the payload words from the payload memory in accordance with the payload processing instructions and assembles the payload words with the header data to form transmit data packets.

Abstract: A method of sharing registers in a processor includes executing a data processing instruction so as to obtain a result of the data processing instruction, which is to be written into a register of the processor. Register sharing information is obtained so as to control writing of the result into the register and/or at least one further register of the processor.

Abstract: A buffer storage memory data scheduler includes a write unit writing data objects to the memory, which unit receives data packets from a data source at a variable transmission rate, calculates attribute data for each received packet, and writes the packet data to the memory as a data object string including linked data objects. The string includes pointer data for linking the objects, calculated attribute data, and packet payload data. The write unit inserts filling objects into the memory between linked data objects to compensate for the variable rate when writing the string to the memory. The write unit increments a counter when the string is written. A time out signaling unit signals to a data processing unit that a buffer-stored data/filling object is ready to be read when the counter reaches a value. The signaling unit decrements the counter corresponding to the data in the object.

Abstract: A device (1) to control processing of data elements (data_i), in which a thread is assigned to each data element (data_i), comprises a first unit (CS), which, during a first cycle, fetches an instruction (cs_ir_s) that is entered in the context of the thread assigned to the incoming data element (data_i), a second unit (IF), which, during a second cycle, fetches an instruction (if_ir_s) that succeeds a stipulated instruction in a stipulated thread, and a third unit (ID), which, during the second cycle, decodes the instruction prescribed for processing of the data element (data_i) and generates a data element processing signal (dec_o).

Abstract: A clock synchronization circuit for synchronizing a first clock signal and a second clock signal for data transfer from a first function block, which is clocked by the first clock signal, to a second function block which is clocked by the second clock signal, where the clock synchronization circuit has a sampling unit for sampling the second clock signal using the first clock signal in order to generate samples and edge detection values of the sampled second clock signal, a logic circuit for outputting the generated edge detection values as a reconstructed clock signal and generating an Edge-too-Early signal and an Edge-too-Late signal; and a signal delay circuit, which delays the reconstructed second clock signal on the bases of the Edge-too-Early signal or the Edge-too-Late signal.

Abstract: The invention provides a data processing apparatus having a data input unit (108) for inputting data, at least one processor unit (107) for carrying out data processing steps (201, 201a, 201b) for the input data, at least one memory unit (402) for storing processed data, the data being able to be written to and read from the memory unit (402) on the basis of a write control signal (101) and a read control signal (102), and a data output unit (109) for outputting stored data, the write control signal (101) being able to be prescribed independently of the timing of the read control signal (102).

Abstract: A multithread processor with synchronization of a command flow, with an associated data flow and with generation of a memory-triggered context switch signal comprises a synchronization device configured, when receiving a load cycle indicator flag with a positive logic signal level from a memory read access unit, to load and buffer in a synchronized fashion an associated context identifier and a target register identifier and to forward the context identifier and the target register identifier to a downstream pipeline stage and, when receiving a validity signal with a positive logic signal level from a memory system, to load and buffer in a synchronized fashion an associated memory value, and to forward the memory value to the pipeline stage. The processor comprises further a logic circuit generating, when the load cycle indicator flag with a positive logic signal level and the validity signal are received, a context switch signal with a negative logic signal level.

Abstract: A multithread processor for the data processing of a plurality of threads, each being provided with a dedicated context, comprises a switching table.

Abstract: The invention relates to a device to be used with a scheduling method, and to a scheduling method, in particular a context scheduling method, comprising the steps of performing a scheduling for threads to be executed by a multithreaded processor, wherein the scheduling is performed as a function of index variables assigned to the threads. That thread whose index variable has the highest, or—in an alternative—the lowest value may be selected as the respective thread to be executed by the processor.

Abstract: The invention relates to a device to be used with a thread scheduling method, and to a thread scheduling method comprising the steps of performing a scheduling for threads to be executed by a multithreaded (MT) processor (11), characterized in that the scheduling is performed as a function of a variable (idle) representing the processor idle time.

Abstract: A clock synchronization circuit for synchronizing a first clock signal (?1) and a second clock signal (?2) for data transfer from a first function block (2), which is clocked by the first clock signal (?D) at a relatively high clock frequency (f?1), to a second function block (3), which is clocked by the second clock signal (?2) at a relatively low clock frequency (f?2), where the clock synchronization circuit (24) has a sampling unit (30) for sampling the second clock signal (?2) using the first clock signal (?1) in order to generate samples (S) and edge detection values (E) of the sampled second clock signal (?2), a logic circuit (38), clocked using the first clock signal (?1), for outputting the generated samples (S) or the generated edge detection values (E) as a reconstructed second clock signal (?2?) in the time frame of the first clock signal (?1) at an output of the logic circuit (38), where the output (42) of the logic circuit is reset after outputting a value (S, E) until the logic circuit (38) rece

Abstract: A buffer storage memory data scheduler includes a write unit writing data objects to the memory, which unit receives data packets from a data source at a variable transmission rate, calculates attribute data for each received packet, and writes the packet data to the memory as a data object string including linked data objects. The string includes pointer data for linking the objects, calculated attribute data, and packet payload data. The write unit inserts filling objects into the memory between linked data objects to compensate for the variable rate when writing the string to the memory. The write unit increments a counter when the string is written. A time out signaling unit signals to a data processing unit that a buffer-stored data/filling object is ready to be read when the counter reaches a value. The signaling unit decrements the counter corresponding to the data in the object.

Abstract: Multichannel processor for processing data of multi-protocol data packets, comprising (a) a number of input ports (2) for receiving received data packets in parallel, which can be selected in each case by means of an input port number; (b) at least one multiplexer (3) connected to the input ports (2), which switches through the data present at the selected input port word by word; (c) at least one first programmable data processing unit (4), which separates the sequence of data words switched through by the multiplexer (3) into data packet header words and into data packet payload words in accordance with a sorting program selected in accordance with the input port number; (d) a buffer management unit (44) which writes the data packet payload words of a received data packet into an addressable payload memory (47) and generates localization data which specify the corresponding memory area; (e) a descriptor generator unit (43) for generating data packet descriptors which in each case contain a header assembled

Abstract: A device (1) to control processing of data elements (data_i), in which a thread is assigned to each data element (data_i), comprises a first unit (CS), which, during a first cycle, fetches an instruction (cs_ir_s) that is entered in the context of the thread assigned to the incoming data element (data_i), a second unit (IF), which, during a second cycle, fetches an instruction (if_ir_s) that succeeds a stipulated instruction in a stipulated thread, and a third unit (ID), which, during the second cycle, decodes the instruction prescribed for processing of the data element (data_i) and generates a data element processing signal (dec_o).