Patents by Inventor Lorenzo Longo
Lorenzo Longo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9338040Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.Type: GrantFiled: February 5, 2015Date of Patent: May 10, 2016Assignee: BROADCOM CORPORATIONInventors: Lorenzo Longo, Vivek Telang
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Publication number: 20150146766Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.Type: ApplicationFiled: February 5, 2015Publication date: May 28, 2015Applicant: BROADCOM CORPORATIONInventors: Lorenzo Longo, Vivek Telang
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Patent number: 8964818Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.Type: GrantFiled: January 11, 2013Date of Patent: February 24, 2015Assignee: Broadcom CorporationInventors: Lorenzo Longo, Vivek Telang
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Patent number: 8886840Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fiber Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.Type: GrantFiled: June 21, 2013Date of Patent: November 11, 2014Assignee: Broadcom CorporationInventors: Ichiro Fujimori, Tuan Hoang, Ben Tan, Lorenzo Longo
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Publication number: 20140153620Abstract: A short reach communication system includes a plurality of communication SERDES that communicate data over a short reach channel medium such as a backplane connection (e.g., PCB trace) between, for example, chips located on a common PCB. A multi-level modulated data signal is generated to transmit/receive data over the short reach channel medium. Multi-level modulated data signals, such as four-level PAM, reduce the data signal rate therefore reducing insertion loss, power, complexity of the circuits and required chip real estate.Type: ApplicationFiled: January 11, 2013Publication date: June 5, 2014Applicant: BROADCOM CORPORATIONInventors: Lorenzo Longo, Vivek Telang
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Patent number: 8669646Abstract: Methods and apparatus for improved electromagnetic interference (EMI) shielding and thermal performance in integrated circuit (IC) packages are described. A die-up or die-down package includes a protective lid, a plurality of ground posts, an IC die, and a substrate. The substrate includes a plurality of ground planes. The IC die is mounted to the substrate. Plurality of ground posts is coupled to plurality of ground planes that surround IC die. Protective lid is coupled to plurality of ground posts. The plurality of ground posts and the protective lid from an enclosure structure that substantially encloses the IC die, and shields EMI from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.Type: GrantFiled: May 31, 2011Date of Patent: March 11, 2014Assignee: Broadcom CorporationInventors: Mohammad Tabatabai, Abbas Amirichimeh, Lorenzo Longo
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Publication number: 20130279551Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.Type: ApplicationFiled: June 21, 2013Publication date: October 24, 2013Inventors: Ichiro Fujimori, Tuan Hoang, Ben Tan, Lorenzo Longo
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Patent number: 8473640Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fiber Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.Type: GrantFiled: June 6, 2012Date of Patent: June 25, 2013Assignee: Broadcom CorporationInventors: Ichiro Fujimori, Tuan Hoang, Ben Tan, Lorenzo Longo
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Publication number: 20120306061Abstract: Methods and apparatus for improved electromagnetic interference (EMI) shielding and thermal performance in integrated circuit (IC) packages are described. A die-up or die-down package includes a protective lid, a plurality of ground posts, an IC die, and a substrate. The substrate includes a plurality of ground planes. The IC die is mounted to the substrate. Plurality of ground posts is coupled to plurality of ground planes that surround IC die. Protective lid is coupled to plurality of ground posts. The plurality of ground posts and the protective lid from an enclosure structure that substantially encloses the IC die, and shields EMI from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: Broadcom CorporationInventors: Mohammad Tabatabai, Abbas Amirichimeh, Lorenzo Longo
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Publication number: 20120243587Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.Type: ApplicationFiled: June 6, 2012Publication date: September 27, 2012Applicant: BROADCOM CORPORATIONInventors: Ichiro Fujimori, Tuan Hoang, Ben Tan, Lorenzo Longo
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Patent number: 8230114Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.Type: GrantFiled: October 29, 2002Date of Patent: July 24, 2012Assignee: Broadcom CorporationInventors: Ichiro Fujimori, Tuan Hoang, Ben Tan, Lorenzo Longo
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Patent number: 7961781Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.Type: GrantFiled: August 10, 2007Date of Patent: June 14, 2011Assignee: Broadcom CorporationInventors: Vivek Telang, Vasudevan Parthasarathy, Sudeep Bhoja, Hong Chen, Afshin Momtaz, Chung-Jue Chen, Ali Ghiasi, Michael Furlong, Lorenzo Longo
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Publication number: 20080049847Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.Type: ApplicationFiled: August 10, 2007Publication date: February 28, 2008Applicant: BROADCOM CORPORATIONInventors: Vivek Telang, Vasudevan Parthasarathy, Sudeep Bhoja, Hong Chen, Afshin Momtaz, Chung-Jue Chen, Ali Ghiasi, Michael Furlong, Lorenzo Longo
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Publication number: 20040030805Abstract: A system and method are disclosed for supporting 10 Gigabit digital serial communications. Many of the functional components and sublayers of a 10 Gigabit digital serial communications transceiver module are integrated into a single IC chip using the same CMOS technology throughout the single chip. The single chip includes a PMD transmit/receive CMOS sublayer, a PMD PCS CMOS sublayer, a XGXS PCS CMOS sublayer, and a XAUI transmit/receive CMOS sublayer. The single chip supports both 10 Gigabit Ethernet operation and 10 Gigabit Fibre Channel operation. The single chip interfaces to a MAC, an optical PMD, and non-volatile memory.Type: ApplicationFiled: October 29, 2002Publication date: February 12, 2004Inventors: Ichiro Fujimori, Tuan Hoang, Ben Tan, Lorenzo Longo
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Patent number: 6522277Abstract: A circuit, system, and method are provided for imparting improved randomness into the selection of components or elements of a data converter, such as a D/A converter. The elements are intended to be of equal value, however, regardless of whether they are or not. A circuit is used to randomly select subsets of elements according to a bi-directional selection technique in order to effectively rending the elements or components of equal value. Associated with each component is a switch, and a subset of the plurality of components are correspondingly switched in successive order progressing in a first direction and, subsequently, in successive order progressing in a second direction opposite the first direction. Connecting components in a first direction from left-to-right follows by selecting components in a second direction from right-to-left, and then again selecting components in the first direction from left-to-right, and so forth.Type: GrantFiled: February 5, 2001Date of Patent: February 18, 2003Assignees: Asahi Kasei Microsystems, Inc., Broadcom CorporationInventors: Ichiro Fujimori, Armond Hairapetian, Lorenzo Longo
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Publication number: 20020105453Abstract: A circuit, system, and method are provided for imparting improved randomness into the selection of components or elements of a data converter, such as a D/A converter. The elements are intended to be of equal value, however, regardless of whether they are or not. A circuit is used to randomly select subsets of elements according to a bi-directional selection technique in order to effectively rending the elements or components of equal value. Associated with each component is a switch, and a subset of the plurality of components are correspondingly switched in successive order progressing in a first direction and, subsequently, in successive order progressing in a second direction opposite the first direction. Connecting components in a first direction from left-to-right follows by selecting components in a second direction from right-to-left, and then again selecting components in the first direction from left-to-right, and so forth.Type: ApplicationFiled: February 5, 2001Publication date: August 8, 2002Inventors: Ichiro Fujimori, Armond Hairapetian, Lorenzo Longo