Patents by Inventor Loris Vendrame
Loris Vendrame has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7563684Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component havinType: GrantFiled: November 1, 2005Date of Patent: July 21, 2009Inventors: Fabio Pellizzer, Giulio Casagrande, Roberto Gastaldi, Loris Vendrame, Augusto Benvenuti, Tyler Lowrey
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Patent number: 7483296Abstract: A memory device is proposed. The memory device includes a plurality of memory cells, wherein each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element and a bipolar element. The memory device further includes control means for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.Type: GrantFiled: September 22, 2005Date of Patent: January 27, 2009Inventors: Ferdinando Bedeschi, Fabio Pellizzer, Augusto Benvenuti, Loris Vendrame, Paola Zuliani
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Patent number: 7352192Abstract: A method and a relative test structure for measuring the coupling capacitance between two interconnect lines exploits the so-called cross-talk effect and keeps an interconnect line at a constant reference voltage. This approach addresses the problem of short-circuit currents that affect known test structures, and allows a direct measurement of the coupling capacitance between the two interconnect lines. Capacitance measurements may also be used for determining points of interruption of interconnect lines. When a line is interrupted, the measured coupling capacitance is the capacitance of a single conducting branch. The position of points of interruption of an interconnect line is determined by measuring the coupling capacitance of all segments of the line with a second conducting line.Type: GrantFiled: April 30, 2004Date of Patent: April 1, 2008Assignee: STMicroelectronics S.r.l.Inventors: Luca Bortesi, Loris Vendrame, Alessandro Bogliolo
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Publication number: 20060062051Abstract: A memory device is proposed. The memory device includes a plurality of memory cells, wherein each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element and a bipolar element. The memory device further includes control means for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.Type: ApplicationFiled: September 22, 2005Publication date: March 23, 2006Inventors: Ferdinando Bedeschi, Fabio Pellizzer, Augusto Benvenuti, Loris Vendrame, Paola Zuliani
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Publication number: 20060049392Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component havinType: ApplicationFiled: November 1, 2005Publication date: March 9, 2006Applicants: STMicroelectronics S.r.l., Ovonyx Inc.Inventors: Fabio Pellizzer, Giulio Casagrande, Roberto Gastaldi, Loris Vendrame, Augusto Benvenuti, Tyler Lowrey
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Patent number: 6989580Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component havinType: GrantFiled: October 7, 2003Date of Patent: January 24, 2006Assignees: STMicroelectronics S.r.l., Ovonyx, Inc.Inventors: Fabio Pellizzer, Giulio Casagrande, Roberto Gastaldi, Loris Vendrame, Augusto Benvenuti, Tyler Lowrey
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Patent number: 6876033Abstract: An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.Type: GrantFiled: June 25, 2003Date of Patent: April 5, 2005Assignee: STMicroelectronics S.r.l.Inventors: Paolo Cappelletti, Paolo Ghezzi, Alfonso Maurelli, Loris Vendrame, Paola Zabberoni
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Publication number: 20040227527Abstract: A method and a relative test structure for measuring the coupling capacitance between two interconnect lines exploits the so-called cross-talk effect and keeps an interconnect line at a constant reference voltage. This approach addresses the problem of short-circuit currents that affect known test structures, and allows a direct measurement of the coupling capacitance between the two interconnect lines. Capacitance measurements may also be used for determining points of interruption of interconnect lines. When a line is interrupted, the measured coupling capacitance is the capacitance of a single conducting branch. The position of points of interruption of an interconnect line is determined by measuring the coupling capacitance of all segments of the line with a second conducting line.Type: ApplicationFiled: April 30, 2004Publication date: November 18, 2004Applicant: STMicroelectronics S.r.l.Inventors: Luca Bortesi, Loris Vendrame, Alessandro Bogliolo
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Publication number: 20040130000Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component havinType: ApplicationFiled: October 7, 2003Publication date: July 8, 2004Applicants: STMicroelectronics S.r.l., Ovonyx Inc.Inventors: Fabio Pellizzer, Giulio Casagrande, Roberto Gastaldi, Loris Vendrame, Augusto Benvenuti, Tyler Lowrey
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Publication number: 20040061168Abstract: An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.Type: ApplicationFiled: June 25, 2003Publication date: April 1, 2004Applicant: STMICROELECTRONICS S.r.IInventors: Paolo Cappelletti, Paolo Ghezzi, Alfonso Maurelli, Loris Vendrame, Paola Zabberoni
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Patent number: 6700226Abstract: A transistor includes a substrate region (14) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region (13) of the first type (P+) of conductivity inside the substrate region (14) and adjacent to a first terminal (C) of the transistor, a well (11) of second type (N) of conductivity placed inside the substrate region (14), wherein the well (11) of second type (N) of conductivity includes at least a second contact region (12) of a second type of conductivity (N+) adjacent to a region of a second terminal (B) of the transistor, and a plurality of third contact regions (10) of the first type of conductivity (P+) adjacent to a plurality of regions of a third terminal (E1, . . . , E3) of the transistor interposed each one (10) and other (12) by proper insulating shapes (20).Type: GrantFiled: December 27, 2001Date of Patent: March 2, 2004Assignee: STMicroelectronic S.r.l.Inventors: Loris Vendrame, Paolo Caprara, Giorgio Oddone, Antonio Barcella
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Patent number: 6670229Abstract: A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS transistor formed in said substrate, an NMOS transistor formed in said substrate, and the bipolar transistor.Type: GrantFiled: February 15, 2002Date of Patent: December 30, 2003Assignee: STMicroelectronics S.r.l.Inventors: Loris Vendrame, Paolo Ghezzi
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Publication number: 20020149089Abstract: A transistor includes a substrate region (14) of a first type (P) of conductivity in a semiconductor material layer of the same type (P) of conductivity, at least a first contact region (13) of the first type (P+) of conductivity inside the substrate region (14) and adjacent to a first terminal (C) of the transistor, a well (11) of second type (N) of conductivity placed inside the substrate region (14), wherein the well (11) of second type (N) of conductivity includes at least a second contact region (12) of a second type of conductivity (N+) adjacent to a region of a second terminal (B) of the transistor, and a plurality of third contact regions (10) of the first type of conductivity (P+) adjacent to a plurality of regions of a third terminal (E1, . . . , E3) of the transistor interposed each one (10) and other (12) by proper insulating shapes (20).Type: ApplicationFiled: December 27, 2001Publication date: October 17, 2002Applicant: STMICROELECTRONICS S.r.l.Inventors: Loris Vendrame, Paolo Caprara, Giorgio Oddone, Antonio Barcella
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Publication number: 20020074607Abstract: A bipolar transistor is produced by processes employed in the manufacture of CMOS nonvolatile memory devices, and is part of an integrated circuit. The integrated circuit includes a semiconductor substrate having a first type of conductivity, a PMOS transistor formed in said substrate, an NMOS transistor formed in said substrate, and the bipolar transistor.Type: ApplicationFiled: February 15, 2002Publication date: June 20, 2002Applicant: STMicroelectronics, S.r.I.Inventors: Loris Vendrame, Paolo Ghezzi