Abstract: Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.

Abstract: Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.

Abstract: In an embodiment, a read-only memory array includes a plurality of word lines, a plurality of bit-lines including first and second bit-lines, and a plurality of memory cells configured to represent data values. Each memory cell can include a transistor having a control terminal coupled to one of the plurality of word lines, a drain terminal, and a source terminal. Connections associated with the drain and source terminals of a particular memory cell can determine a data value represented by the memory cell. The memory cells of the plurality of memory cells that are coupled to less than two bit-lines are configured to represent one values.

Abstract: Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.

Abstract: A circuit includes a first negative feed back loop coupled to a virtual Vvdd power rail and a true Vdd power rail. A second negative feed back loop is coupled to the virtual Vvss power rail and a true Vss power rail. The virtual rail to virtual rail voltage difference is regulated at the highest threshold voltage between pull-up and pull-down transistors of a memory cell.

Abstract: A high-density non-volatile memory array. In one aspect of the invention, a memory array circuit includes a plurality of word lines, a plurality of bit-lines, and a plurality of memory cell transistors. The gate of each memory cell transistor is connected to one of the word lines, and the drains and sources of each memory cell transistor are connected only to the bit-lines.

Abstract: Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.

Abstract: A high-density non-volatile memory array. In one aspect of the invention, a memory array circuit includes a plurality of word lines, a plurality of bit-lines, and a plurality of memory cell transistors. The gate of each memory cell transistor is connected to one of the word lines, and the drains and sources of each memory cell transistor are connected only to the bit-lines.