Patents by Inventor Louis B. Capps, Jr.

Louis B. Capps, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11163850
    Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer includes receiving and storing a plurality of different data patterns anticipated to be encountered by a processor unit of a data processing system corresponding to a particular application being processed. Responsive to receiving a read request for data, the requested data is read from a memory subsystem, and the read data is compared by the memory subsystem to the stored data patterns. Responsive to determining that the read data matches at least one of the stored data patterns, the memory subsystem replaces the matching read data with a pattern tag corresponding to the matching data pattern. The pattern tag is transmitted over a communication link in response to the request.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Louis B. Capps, Jr., Daniel M. Dreps, Luis A. Lastras-Montano, Michael J. Shapiro
  • Publication number: 20200233909
    Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer includes receiving and storing a plurality of different data patterns anticipated to be encountered by a processor unit of a data processing system corresponding to a particular application being processed. Responsive to receiving a read request for data, the requested data is read from a memory subsystem, and the read data is compared by the memory subsystem to the stored data patterns. Responsive to determining that the read data matches at least one of the stored data patterns, the memory subsystem replaces the matching read data with a pattern tag corresponding to the matching data pattern. The pattern tag is transmitted over a communication link in response to the request.
    Type: Application
    Filed: April 6, 2020
    Publication date: July 23, 2020
    Inventors: Robert H. Bell, JR., Louis B. Capps, JR., Daniel M. Dreps, Luis A. Lastras-Montano, Michael J. Shapiro
  • Patent number: 10025590
    Abstract: A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Louis B. Capps, Jr., Ronald E. Newhart, Thomas E. Cook, Robert H. Bell, Jr., Michael J. Shapiro
  • Publication number: 20180165377
    Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer includes receiving and storing a plurality of different data patterns anticipated to be encountered by a processor unit of a data processing system corresponding to a particular application being processed. Responsive to receiving a read request for data, the requested data is read from a memory subsystem, and the read data is compared by the memory subsystem to the stored data patterns. Responsive to determining that the read data matches at least one of the stored data patterns, the memory subsystem replaces the matching read data with a pattern tag corresponding to the matching data pattern. The pattern tag is transmitted to the processor unit instead of the requested data as a response to the read request, and the processor unit replaces the pattern tag with the corresponding data pattern.
    Type: Application
    Filed: January 27, 2018
    Publication date: June 14, 2018
    Inventors: Robert H. Bell, JR., Louis B. Capps, JR., Daniel M. Dreps, Luis A. Lastras-Montano, Michael J. Shapiro
  • Patent number: 9830557
    Abstract: Various embodiments provide systems, computer program products and computer implemented methods. Some embodiments include a method of updating an expert corpus set, including obtaining a query from a user, obtaining a raw data source, determining a relevance score for the raw data source with respect to the query, by performing actions including creating a first vector of statistical variables for the query using at least one natural language processing (NLP) socket, the statistical variables having category types, creating a second vector for the first raw data source, having category types that are the same as those for the query and generating a hypothesis regarding the relevance of the raw data source, testing the hypothesis by comparing relative statistical variables, calculating a gradient between the vectors to determine the relevance score and updating the expert corpus set with the raw data in response to the relevance score exceeds a threshold.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Aaron K. Baughman, Louis B. Capps, Jr., Barry M. Graham, Jennifer R. Mahle
  • Publication number: 20170075690
    Abstract: A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.
    Type: Application
    Filed: November 23, 2016
    Publication date: March 16, 2017
    Inventors: Louis B. Capps, JR., Ronald E. Newhart, Thomas E. Cook, Robert H. Bell, JR., Michael J. Shapiro
  • Patent number: 9507640
    Abstract: A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: November 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Louis B. Capps, Jr., Ronald E. Newhart, Thomas E. Cook, Robert H. Bell, Jr., Michael J. Shapiro
  • Patent number: 9336497
    Abstract: Various embodiments provide systems, computer program products and computer implemented methods. Some embodiments include a method of updating an expert corpus set, including obtaining a query from a user, obtaining a raw data source, determining a relevance score for the raw data source with respect to the query, by performing actions including creating a first vector of statistical variables for the query using at least one natural language processing (NLP) socket, the statistical variables having category types, creating a second vector for the first raw data source, having category types that are the same as those for the query and generating a hypothesis regarding the relevance of the raw data source, testing the hypothesis by comparing relative statistical variables, calculating a gradient between the vectors to determine the relevance score and updating the expert corpus set with the raw data in response to the relevance score exceeds a threshold.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: May 10, 2016
    Assignee: International Business Machines Corporation
    Inventors: Aaron K. Baughman, Louis B. Capps, Jr., Barry M. Graham, Jennifer R. Mahle
  • Publication number: 20160078039
    Abstract: Various embodiments provide systems, computer program products and computer implemented methods. Some embodiments include a method of updating an expert corpus set, including obtaining a query from a user, obtaining a raw data source, determining a relevance score for the raw data source with respect to the query, by performing actions including creating a first vector of statistical variables for the query using at least one natural language processing (NLP) socket, the statistical variables having category types, creating a second vector for the first raw data source, having category types that are the same as those for the query and generating a hypothesis regarding the relevance of the raw data source, testing the hypothesis by comparing relative statistical variables, calculating a gradient between the vectors to determine the relevance score and updating the expert corpus set with the raw data in response to the relevance score exceeds a threshold.
    Type: Application
    Filed: November 19, 2015
    Publication date: March 17, 2016
    Inventors: Aaron K. Baughman, Louis B. Capps, JR., Barry M. Graham, Jennifer R. Mahle
  • Publication number: 20150193682
    Abstract: Various embodiments provide systems, computer program products and computer implemented methods. Some embodiments include a method of updating an expert corpus set, including obtaining a query from a user, obtaining a raw data source, determining a relevance score for the raw data source with respect to the query, by performing actions including creating a first vector of statistical variables for the query using at least one natural language processing (NLP) socket, the statistical variables having category types, creating a second vector for the first raw data source, having category types that are the same as those for the query and generating a hypothesis regarding the relevance of the raw data source, testing the hypothesis by comparing relative statistical variables, calculating a gradient between the vectors to determine the relevance score and updating the expert corpus set with the raw data in response to the relevance score exceeds a threshold.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 9, 2015
    Applicant: International Business Machines Corporation
    Inventors: Aaron K. Baughman, Louis B. Capps, JR., Barry M. Graham, Jennifer R. Mahle
  • Patent number: 8886918
    Abstract: A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values for each thread as a tag in the thread's instructions, tagged instructions from different threads that are dispatched through the system are allocated system resources based on the tagged priority values assigned to the respective instruction threads. Priority values for individual threads may be updated with control software which tests thread performance and uses the test results to apply predetermined adjustment policies.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: November 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Louis B. Capps, Jr., Robert H. Bell, Jr.
  • Patent number: 8495342
    Abstract: A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Louis B. Capps, Jr., Michael J. Shapiro, Robert H. Bell, Jr., Thomas E. Cook, William E. Burky
  • Publication number: 20120002812
    Abstract: Secure communication of data between devices includes encrypting unencrypted data at a first device by reordering unencrypted bits provided in parallel on a device bus, including data and control bits, from an unencrypted order to form encrypted data including a plurality of encrypted bits in parallel in an encrypted order defined by a key. The encrypted data may be transmitted to another device where the encrypted data is decrypted by using the key to order the encrypted bits to restore the unencrypted order thereby to reform the unencrypted data.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert H. Bell, JR., Louis B. Capps, JR., Michael J. Shapiro
  • Patent number: 7962770
    Abstract: A method, system and program are provided for dynamically reconfiguring a pipelined processor to operate with reduced power consumption without reducing existing performance. By monitoring or detecting the performance of individual units or stages in the processor as they execute a given workload, each stage may use high-performance circuitry until such time as a drop in the throughput performance is detected, at which point the stages are reconfigured to use lower-performance circuitry so as to meet the reduced performance throughput requirements using less power. By configuring the processor to back off from high-performance designs to low-performance designs to meet the detected performance characteristics of the executing workload warrant, power dissipation may be optimized.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Louis B. Capps, Jr., Robert H. Bell, Jr., Michael J. Shapiro
  • Patent number: 7870337
    Abstract: A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jr., Louis B. Capps, Jr., Thomas E. Cook, Michael J. Shapiro, Naresh Nayar
  • Publication number: 20100153956
    Abstract: A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 17, 2010
    Inventors: Louis B. Capps, JR., Ronald E. Newhart, Thomas E. Cook, Robert H. Bell, JR., Michael J. Shapiro
  • Publication number: 20100153700
    Abstract: A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.
    Type: Application
    Filed: December 16, 2008
    Publication date: June 17, 2010
    Inventors: Louis B. Capps, JR., Michael J. Shapiro, Robert H. Bell, JR., Thomas E. Cook, William E. Burky
  • Patent number: 7667470
    Abstract: A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: February 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Louis B. Capps, Jr., Glenn G. Daves, Anand Haridass, Ronald E. Newhart, Michael J. Shapiro
  • Publication number: 20090164812
    Abstract: A method, system and program are provided for dynamically reconfiguring a pipelined processor to operate with reduced power consumption without reducing existing performance. By monitoring or detecting the performance of individual units or stages in the processor as they execute a given workload, each stage may use high-performance circuitry until such time as a drop in the throughput performance is detected, at which point the stages are reconfigured to use lower-performance circuitry so as to meet the reduced performance throughput requirements using less power. By configuring the processor to back off from high-performance designs to low-performance designs to meet the detected performance characteristics of the executing workload warrant, power dissipation may be optimized.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 25, 2009
    Inventors: Louis B. Capps, JR., Robert H. Bell, JR., Michael J. Shapiro
  • Publication number: 20090138682
    Abstract: A method, system and program are provided for dynamically assigning priority values to instruction threads in a computer system based on one or more predetermined thread performance tests, and using the assigned instruction priorities to determine how resources are used in the system. By storing the assigning priority values for each thread as a tag in the thread's instructions, tagged instructions from different threads that are dispatched through the system are allocated system resources based on the tagged priority values assigned to the respective instruction threads. Priority values for individual threads may be updated with control software which tests thread performance and uses the test results to apply predetermined adjustment policies.
    Type: Application
    Filed: November 28, 2007
    Publication date: May 28, 2009
    Inventors: Louis B. Capps, JR., Robert H. Bell, JR.