Abstract: A quadrature based embedded servo control system is provided to realize a high track density, high-performance hard disk drive system. Each data sector includes a gray code field spanning the entire width of the data track and a quad-servo burst pattern having first, second, third, and fourth servo burst fields distributed along the length of a portion of the data sector. The center point of the first, second, third, and fourth servo bursts are sequentially offset from the adjacent burst by a radial distance equivalent to one-half of the data track width. The quad-servo burst pattern is used with a track-following algorithm based on the quadrature value of (A+B)-(C+D) to obtain a substantially increased servo lock range.

Abstract: The read/write channel is programmatically adaptable to the media used for storing data in response to data signals and the read/write head used to transfer the data signals to and from the media. Adaptability is provided by progammable signal processing elements in the read/write channel. The programmable elements include a read threshold element for determining whether data signals transferred from the media exceed a data discrimination level determined by a first programmable value, and a data window element for determining whether data signals transferred from the media occur within a data signal window whose timing, relative to a data clock signal, is determined by the second programmable value. Additional programmable elements include an amplifier element that is programmed to provide a corresponding level of write current and a precompensation block for providing data signal precompensation.

Abstract: A disk drive control architecture provides for the storage and retrieval of data with respect to a rotating media and for the transfer of data with respect to a host in response to host commands. The control architecture provides for the execution of a plurality of background processes for controlling the spin speed of the rotating media, controlling the positioning of the sensor and controlling the reading and writing of data with respect to the rotating media. The control architecture further provides for foreground processes for controlling the background processes. The foreground processes include an interface task, for coordinating the background processes in the execution of host commands and a monitor task integral to the interface task such that the monitor task is capable of implementing diagnostic commands capable of accessing all of the resources of the control architecture.

Abstract: The control system manages the storage and retrieval of data with respect to a rotating media, wherein an actuator is utilized in the selection of data for storage and retrieval. The control system includes a low level media control circuit that permits the selection of the rotational position of the rotating media and an actuator control circuit that permits the selection of the position of the actuator with respect to the rotating media. A system controller is utilized to direct the operation of the low level media and actuator control circuits whereby the system controller specifies and adjusts, in real time, the incremental selection of the rotational position of the rotating media and the position of the actuator with respect to the rotating media.

Abstract: Control and synchronization of a polyphase, brushless DC motor (used for a hard-disk system) during initial start-up of the motor, is effected by monitoring rotor position using a high-frequency commutation: A short current pulse is applied to each power phase of the motor, and motor current conducted in response thereto, is measured to determine therefrom positional information of the rotor. From such positional information the identity of the appropriate motor phase to which is applied a torque-producing current is determined. Cycles of high-frequency commutation and application of torque-producing are performed, until the rotational speed of the rotor has attained a predetermined RPM.

Abstract: An address mark whose pattern is distinguishable from information data is produced by generating a number of relatively long pulses followed by a number of relatively shorter pulses. Preferably, a binary "1" is recirculated through a first predetermined number of stages of a shift register (for a first pre-established number of times) and then through a second (different) predetermined number of stages (for a second pre-established number of times). A signal level transition which defines the beginning or end of a pulse in the address mark pattern is generated in response to each binary "1" output from that shift register. The address mark pattern is detected by, preferably, supplying an input signal to be detected to the same aforementioned shift register, detecting n successive longer pulses and then detecting m successive shorter pulses, where n and m are less than the aforementioned first and second pre-established numbers, respectively.

Abstract: A circuit and method for qualifying valid data peaks within a raw readout signal. The raw readout signal is of the type generated when data is retrieved from magnetic storage devices. The raw readout signal is processed through four parallel channels. A first channel includes follow and hold circuitry that follows the signal level of the raw readout signal if the signal level is increasing, and holds the highest previously encountered signal level when the raw readout signal level is decreasing. The follow and hold circuitry also detects the occurrence of a prescribed polarity slope within the raw readout signal, providing the amplitude of the raw readout signal at the point where the slope is detected exceeds the value held in the follow and hold circuitry.