Abstract: An ambient light adjustment (ALA) apparatus, a method and a system therewith are proposed. The ALA apparatus includes a main body having a plurality of edges, one or more light sources, a light blocking layer and a controller. The light source is mounted on at least one edge of the ALA apparatus. The main body comprises at least one light guide plate. The light blocking layer is disposed over a surface of the main body. The controller is coupled to the light source and the light blocking layer. The ALA apparatus further comprises at least one sensor coupled to the controller. The controller controls the light characteristics of the light source and/or the light blockage levels of the light blocking layer to adjust ambient light characteristics, according to a sensed result by the sensor or sensors.

Abstract: A portable analytical device including at least one optical unit and optionally an adapting device are provided. The optical unit includes a light beam receiving area, a sample holder, a light beam exiting area, and a lens component. The adapting device holds the optical unit and an external hand-held computing device (EHCD), such that the optical unit is coupled to the EHCD.

Abstract: A microelectronic 3D packaging structure and a method of manufacturing the same are introduced. The microelectronic 3D packaging structure includes a first board with a plurality of a first edges and disposed with a first electronic device; a second board with a plurality of a second edges and disposed with a second electronic device, wherein at least one second edge of the second board is jointed to at least one first edge of the first board to form a joint line; and a joint connection portion disposed at the joint line of the two adjacent boards and adapted to function as a connection path for transmitting signals.

Abstract: A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.

Abstract: A microelectronic 3D packaging structure and a method of manufacturing the same are introduced. The microelectronic 3D packaging structure includes a first board with a plurality of a first edges and disposed with a first electronic device; a second board with a plurality of a second edges and disposed with a second electronic device, wherein at least one second edge of the second board is jointed to at least one first edge of the first board to form a joint line; and a joint connection portion disposed at the joint line of the two adjacent boards and adapted to function as a connection path for transmitting signals.

Abstract: A method, system, electronic device, and non-transitory computer readable storage medium for behavior based user interface layout display are provided. The method includes: displaying service information on an user interface in the form of a first layout arrangement with a first set of components, receiving a service information request from the user interface, establishing an user profile based on the service information request, reconfiguring the service information based on the user profile, and displaying the reconfigured service information on the user interface in the form of a second layout arrangement with a second set of components. A size of each of the first set and the second set of the components is variable.

Abstract: An ambient light adjustment (ALA) apparatus, a method and a system therewith are proposed. The ALA apparatus includes a main body having a plurality of edges, one or more light sources, a light blocking layer and a controller. The light source is mounted on at least one edge of the ALA apparatus. The main body comprises at least one light guide plate. The light blocking layer is disposed over a surface of the main body. The controller is coupled to the light source and the light blocking layer. The ALA apparatus further comprises at least one sensor coupled to the controller. The controller controls the light characteristics of the light source and/or the light blockage levels of the light blocking layer to adjust ambient light characteristics, according to a sensed result by the sensor or sensors.

Abstract: A portable analytical device including at least one optical unit and optionally an adapting device are provided. The optical unit includes a light beam receiving area, a sample holder, a light beam exiting area, and a lens component. The adapting device holds the optical unit and an external hand-held computing device (EHCD), such that the optical unit is coupled to the EHCD.

Abstract: Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.

Abstract: A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.

Abstract: Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.

Abstract: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.

Abstract: A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.

Abstract: Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.

Abstract: A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.

Abstract: Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.

Abstract: Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

Abstract: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.

Abstract: Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.

Abstract: An apparatus and method for manufacturing low-cost high-density compact active inductor module using existing DRAM, SRAM and logic process integration. The elements of the active inductor modules are formed by three semiconductor devices including nMOS devices, deep-trench capacitors and a polysilicon or TaN resistor. The active inductor modules can be connected in a parallel and/or serial configuration to obtain a wide range of inductance values. The modular active inductors can be advantageously stored in an ASIC library to facilitate a flexible and convenient circuit design.