Patents by Inventor Louis Nicholas Hutter

Louis Nicholas Hutter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200135489
    Abstract: A method for making a semiconductor device may include forming a superlattice layer and an adjacent semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include diffusing nitrogen into the superlattice layer.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, LOUIS NICHOLAS HUTTER, III
  • Publication number: 20010019865
    Abstract: A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.
    Type: Application
    Filed: February 2, 2001
    Publication date: September 6, 2001
    Inventors: John P. Erdeljac, Louis Nicholas Hutter, M. Ali Khatibzadeh, John Kenneth Arch
  • Patent number: 6284617
    Abstract: A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: September 4, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: John P. Erdeljac, Louis Nicholas Hutter, M. Ali Khatibzadeh, John Kenneth Arch
  • Patent number: 6236101
    Abstract: A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: May 22, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: John P. Erdeljac, Louis Nicholas Hutter, M. Ali Khatibzadeh, John Kenneth Arch
  • Patent number: 6144100
    Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: November 7, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Chi-Cheong Shen, Donald C. Abbott, Walter Bucksch, Marco Corsi, Taylor Rice Efland, John P. Erdeljac, Louis Nicholas Hutter, Quang Mai, Konrad Wagensohner, Charles Edward Williams