Abstract: An adaptive transmission line termination which includes a variable voltage controlled resistor (16) connected either in series with the sending end of transmission line (10) or in parallel with the receiving end of line (10). The resistance of resistor (16) is varied in dependence upon the half voltage appearing on line (10) in order to match the characteristic impedance of line (10) for the series or source termination case. In the parallel termination case, the resistance of resistor (34) is varied in dependence upon the voltage appearing at the input of gate (14) to match the characteristic impedance of line (10).

Abstract: A novel circuit recovers a carrier signal from a 16 or 64 QAM double sideband suppressed carrier IF signal for use in synchronolus demodulation. A 70 MHz IF signal is fed to a power splitter for distributing the signals to a demodulator and to a quadrupler. The 280 MHz signal from the quadrupler is fed to a surface acoustic wave filter to extract the components of the double sideband suppressed carrier signal and the output therefrom is amplified prior to being divided by four to recover the 70 MHz signal. The 70 MHz signal is delivered to a phase frequency detector which provides an error signal during acquisition to deviate a VCO toward the received frequency and thus obtain very fast acquisition time. When the VCO is locked, the phase frequency detector is disconnected from the summing node of a PLL, and a correlated error polarity adaptive carrier recovery circuit operates the demodulator.

Abstract: The performance of carrier and/or timing recovery circuits which control the recovery of data signals from modulated quadrature-related carrier signals is improved by the use of a phase detector which correlates the two most significant bits of the data signals. This correlation significantly reduces the acquisition time, i.e., the time required for these circuits to acquire synchronous operation. Moreover, this correlation can be advantageously combined with correlations of the most and least significant bits of the data signals to reduce phase jitter as well as reduce the acquisition time.