Abstract: An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface.

Abstract: An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface.

Abstract: A network adapter for allowing packet data to be separated over multiple bus targets, without impact to input/output bus bandwidth or network performance, having: a bus interface circuit; a bus protocol circuit coupled to the bus interface circuit; a burst dispatcher circuit coupled to the bus protocol circuit; a network interface coupled to a read processing circuit and a write processing circuit, wherein the read processing circuit and the write processing circuit are coupled to the burst dispatcher; and, a synchronization and buffering circuit coupled to the bus protocol circuit, the burst dispatcher circuit, the read processing circuit and the write processing circuit.

Abstract: A network adapter for allowing packet data to be separated over multiple bus targets, without impact to input/output bus bandwidth or network performance, having: a bus interface circuit; a bus protocol circuit coupled to the bus interface circuit; a burst dispatcher circuit coupled to the bus protocol circuit; a network interface coupled to a read processing circuit and a write processing circuit, wherein the read processing circuit and the write processing circuit are coupled to the burst dispatcher; and, a synchronization and buffering circuit coupled to the bus protocol circuit, the burst dispatcher circuit, the read processing circuit and the write processing circuit.

Abstract: An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock (mclk), for transferring data between the first and second circuitry and achieving a fast turn-around time between a data request from the mclk domain circuitry and a bus request in the sclk domain. A first FIFO buffer for transferring data from the first circuitry to the second circuitry is provided. Logic associated with the first FIFO to synchronize reads and writes to the first FIFO is also provided. A read Bus Request Enable Generator provides a read bus request enable signal to the first circuitry, and an At_least_x_words_filled Flag Generator provides a plurality of flags, which indicate degrees of fullness of the first FIFO buffer to the second circuitry. A second FIFO buffer transfers data from the second circuitry to the first circuitry. Associated logic for synchronizing reads and writes to the second FIFO buffer is provided.

Abstract: An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock (mclk), for transferring data between the first and second circuitry and achieving a fast turn-around time between a data request from the mclk domain circuitry and a bus request in the sclk domain. A first FIFO buffer for transferring data from the first circuitry to the second circuitry is provided. Logic associated with the first FIFO to synchronize reads and writes to the first FIFO is also provided. A read Bus Request Enable Generator provides a read bus request enable signal to the first circuitry, and an At.sub.-- least.sub.-- x.sub.-- words.sub.-- filled Flag Generator provides a plurality of flags, which indicate degrees of fullness of the first FIFO buffer to the second circuitry. A second FIFO buffer transfers data from the second circuitry to the first circuitry.

Abstract: A network adapter for allowing packet data to be separated over multiple bus targets without impact to input/output bus bandwidth or network performance, having: a bus interface circuit; a bus protocol circuit coupled to the bus interface circuit; a burst dispatcher circuit coupled to the bus protocol circuit; a network interface coupled to a read processing circuit and a write processing circuit, wherein the read processing circuit and the write processing circuit are coupled to the burst dispatcher; and, a synchronization and buffering circuit coupled to the bus protocol circuit, the burst dispatcher circuit, the read processing circuit and the write processing circuit.

Abstract: A network station's elasticity buffer includes a memory core together with write and read pointer logic. The memory core includes a START area and a CONTINUATION area which is a cyclic buffer. Under normal conditions, the read pointer follows the write pointer cyclically in the CONTINUATION area. However, upon detection of a start delimiter or upon station reset, the pointers recenter to the START area. Separate synchronizing logic is provided for each of the two recentering modes to reduce metastability problems caused by asynchronous sampling of data.

Abstract: Apparatus and methods for encoding information characters received by a station from a transmission medium to generate internal code points for retrieval or retransmission by the station. The encoding provides an internal symbol set that is able to pass complete line state information via its internal code points, thereby eliminating the need for extra signals to indicate the current line state. The code points can also report error situations, such as elasticity buffer errors, and can be accepted by the station's transmitter to be encoded and, after appropriate filtering, repeated onto the transmission medium. The internal code points are optimized so that the code point set minimizes the decoding logic at the receiving end, be it the station's Media Access Control function or its transmitter. Furthermore, internally, the station may make use of the internal code points to synchronize the receiver elasticity buffer.