Patents by Inventor Loyde M. Carpenter, Jr.
Loyde M. Carpenter, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11150710Abstract: One embodiment is directed towards an encapsulated device. The encapsulated device includes a device, and a first encapsulation covering the device. The first encapsulation has one or more exterior surfaces. One or more recesses in one or more of the exterior surfaces is configured to receive a second encapsulation.Type: GrantFiled: June 7, 2019Date of Patent: October 19, 2021Assignee: Intersil Americas LLCInventors: Randolph Cruz, Loyde M. Carpenter, Jr., Mark A. Kwoka
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Patent number: 10582617Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.Type: GrantFiled: July 21, 2017Date of Patent: March 3, 2020Assignee: Intersil Americas LLCInventors: Jian Yin, Nikhil Kelkar, Loyde M. Carpenter, Jr., Nattorn Pongratananukul, Patrick J. Selby, Steven R. Rivet, Michael W. Althar
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Patent number: 10317965Abstract: One embodiment is directed towards an encapsulated device. The encapsulated device includes a device, and a first encapsulation covering the device. The first encapsulation has one or more exterior surfaces. One or more recesses in one or more of the exterior surfaces is configured to receive a second encapsulation.Type: GrantFiled: February 17, 2016Date of Patent: June 11, 2019Assignee: INTERSIL AMERICAS LLCInventors: Randolph Cruz, Loyde M. Carpenter, Jr., Mark A. Kwoka
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Publication number: 20170325333Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.Type: ApplicationFiled: July 21, 2017Publication date: November 9, 2017Applicant: Intersil Americas LLCInventors: Jian YIN, Nikhil KELKAR, Loyde M. CARPENTER,, JR., Nattorn PONGRATANANUKUL, Patrick J. SELBY, Steven R. RIVET, Michael W. ALTHAR
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Circuit module such as a high-density lead frame array (HDA) power module, and method of making same
Patent number: 9717146Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.Type: GrantFiled: June 28, 2012Date of Patent: July 25, 2017Assignee: INTERSIL AMERICAS LLCInventors: Jian Yin, Nikhil Kelkar, Loyde M. Carpenter, Jr., Nattorn Pongratananukul, Patrick J. Selby, Steven R. Rivet, Michael W. Althar -
Publication number: 20170077807Abstract: One embodiment is directed towards an encapsulated device. The encapsulated device includes a device, and a first encapsulation covering the device. The first encapsulation has one or more exterior surfaces. One or more recesses in one or more of the exterior surfaces is configured to receive a second encapsulation.Type: ApplicationFiled: February 17, 2016Publication date: March 16, 2017Inventors: Randolph Cruz, Loyde M. Carpenter, JR., Mark A. Kwoka
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Patent number: 8969137Abstract: Embodiments described herein relate to a method of manufacturing a packaged circuit having a solder flow-impeding plug on a lead frame. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch forming a trench. A non-conductive material that is adhesive to the lead frame is applied in the trench, such that the non-conductive material extends across the trench to form the solder flow-impeding plug. One or more components are attached to the internal surface of the lead frame and encapsulated. An external surface of the lead frame is etched at the dividing lines to disconnect different sections of lead frame as a second partial etch.Type: GrantFiled: December 17, 2012Date of Patent: March 3, 2015Assignee: Intersil Americas LLCInventors: Randolph Cruz, Loyde M. Carpenter, Jr.
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Patent number: 8877564Abstract: One embodiment is directed towards a method of manufacturing a packaged circuit. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch. One or more dies are attached to the internal surface of the lead frame and encapsulated. The method also includes partially etching an external surface of the lead frame at the dividing lines to disconnect different sections of lead frame as a second partial etch, wherein the second partial etch removes a laterally wider portion of the lead frame than the first partial etch of the internal surface; and partially etching the external surface of the lead frame as a third partial etch, wherein the third partial etch overlaps a portion of the second partial etch and extends deeper into the lead frame than the second partial etch.Type: GrantFiled: September 27, 2012Date of Patent: November 4, 2014Assignee: Intersil Americas LLCInventors: Randolph Cruz, Loyde M. Carpenter, Jr.
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Patent number: 8871572Abstract: Embodiments described herein relate to manufacturing a device. The method includes etching at least one recess pattern in an internal surface of a lead frame, the at least one recess pattern including a perimeter recess that defines a perimeter of a mounting area. The method also includes attaching a component to the internal surface of the lead frame such that a single terminal of the component is attached in the mounting area and the single terminal covers the perimeter recess, wherein the perimeter recess has a size and shape such that the recess is proximate a perimeter of the single terminal.Type: GrantFiled: December 20, 2012Date of Patent: October 28, 2014Assignee: Intersil Americas LLCInventors: Randolph Cruz, Loyde M. Carpenter, Jr.
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Publication number: 20140175627Abstract: Embodiments described herein relate to manufacturing a device. The method includes etching at least one recess pattern in an internal surface of a lead frame, the at least one recess pattern including a perimeter recess that defines a perimeter of a mounting area. The method also includes attaching a component to the internal surface of the lead frame such that a single terminal of the component is attached in the mounting area and the single terminal covers the perimeter recess, wherein the perimeter recess has a size and shape such that the recess is proximate a perimeter of the single terminal.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: INTERSIL AMERICAS LLCInventors: Randolph Cruz, Loyde M. Carpenter, JR.
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Publication number: 20140097529Abstract: Embodiments described herein relate to a method of manufacturing a packaged circuit having a solder flow-impeding plug on a lead frame. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch forming a trench. A non-conductive material that is adhesive to the lead frame is applied in the trench, such that the non-conductive material extends across the trench to form the solder flow-impeding plug. One or more components are attached to the internal surface of the lead frame and encapsulated. An external surface of the lead frame is etched at the dividing lines to disconnect different sections of lead frame as a second partial etch.Type: ApplicationFiled: December 17, 2012Publication date: April 10, 2014Applicant: INTERSIL AMERICAS LLCInventors: Randolph Cruz, Loyde M. Carpenter, JR.
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Publication number: 20140001618Abstract: One embodiment is directed towards a method of manufacturing a packaged circuit. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch. One or more dies are attached to the internal surface of the lead frame and encapsulated. The method also includes partially etching an external surface of the lead frame at the dividing lines to disconnect different sections of lead frame as a second partial etch, wherein the second partial etch removes a laterally wider portion of the lead frame than the first partial etch of the internal surface; and partially etching the external surface of the lead frame as a third partial etch, wherein the third partial etch overlaps a portion of the second partial etch and extends deeper into the lead frame than the second partial etch.Type: ApplicationFiled: September 27, 2012Publication date: January 2, 2014Applicant: INTERSIL AMERICAS LLCInventors: Randolph Cruz, Loyde M. Carpenter, JR.
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CIRCUIT MODULE SUCH AS A HIGH-DENSITY LEAD FRAME ARRAY (HDA) POWER MODULE, AND METHOD OF MAKING SAME
Publication number: 20130314879Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.Type: ApplicationFiled: June 28, 2012Publication date: November 28, 2013Applicant: INTERSIL AMERICAS LLCInventors: Jian YIN, Nikhil KELKAR, Loyde M. CARPENTER, JR., Nattorn PONGRATANANUKUL, Patrick J. SELBY, Steven R. RIVET, Michael W. ALTHAR -
Patent number: 8206836Abstract: A conductive clip having a riser or post formed along a side thereof includes a notch or opening formed in the riser or post to create a first riser or post section and second riser or post section separated by the notch or opening through which a tiebar extends. The conductive clip organization is will suited for formation as elongated strips of such conductive clips for automated machine assembly of the conductive clips in an integrated circuit package context.Type: GrantFiled: February 3, 2010Date of Patent: June 26, 2012Assignee: Intersil Americas, Inc.Inventors: Loyde M. Carpenter, Jr., Randolph Cruz, Nikhil Kelkar
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Publication number: 20110033724Abstract: A conductive clip having a riser or post formed along a side thereof includes a notch or opening formed in the riser or post to create a first riser or post section and second riser or post section separated by the notch or opening through which a tiebar extends. The conductive clip organization is will suited for formation as elongated strips of such conductive clips for automated machine assembly of the conductive clips in an integrated circuit package context.Type: ApplicationFiled: February 3, 2010Publication date: February 10, 2011Inventors: Loyde M. Carpenter, JR., Randolph Cruz, Nikhil Kelkar