Patents by Inventor Loyde M. Carpenter, Jr.

Loyde M. Carpenter, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11150710
    Abstract: One embodiment is directed towards an encapsulated device. The encapsulated device includes a device, and a first encapsulation covering the device. The first encapsulation has one or more exterior surfaces. One or more recesses in one or more of the exterior surfaces is configured to receive a second encapsulation.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: October 19, 2021
    Assignee: Intersil Americas LLC
    Inventors: Randolph Cruz, Loyde M. Carpenter, Jr., Mark A. Kwoka
  • Patent number: 10582617
    Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: March 3, 2020
    Assignee: Intersil Americas LLC
    Inventors: Jian Yin, Nikhil Kelkar, Loyde M. Carpenter, Jr., Nattorn Pongratananukul, Patrick J. Selby, Steven R. Rivet, Michael W. Althar
  • Patent number: 10317965
    Abstract: One embodiment is directed towards an encapsulated device. The encapsulated device includes a device, and a first encapsulation covering the device. The first encapsulation has one or more exterior surfaces. One or more recesses in one or more of the exterior surfaces is configured to receive a second encapsulation.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: June 11, 2019
    Assignee: INTERSIL AMERICAS LLC
    Inventors: Randolph Cruz, Loyde M. Carpenter, Jr., Mark A. Kwoka
  • Publication number: 20170325333
    Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Applicant: Intersil Americas LLC
    Inventors: Jian YIN, Nikhil KELKAR, Loyde M. CARPENTER,, JR., Nattorn PONGRATANANUKUL, Patrick J. SELBY, Steven R. RIVET, Michael W. ALTHAR
  • Patent number: 9717146
    Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: July 25, 2017
    Assignee: INTERSIL AMERICAS LLC
    Inventors: Jian Yin, Nikhil Kelkar, Loyde M. Carpenter, Jr., Nattorn Pongratananukul, Patrick J. Selby, Steven R. Rivet, Michael W. Althar
  • Publication number: 20170077807
    Abstract: One embodiment is directed towards an encapsulated device. The encapsulated device includes a device, and a first encapsulation covering the device. The first encapsulation has one or more exterior surfaces. One or more recesses in one or more of the exterior surfaces is configured to receive a second encapsulation.
    Type: Application
    Filed: February 17, 2016
    Publication date: March 16, 2017
    Inventors: Randolph Cruz, Loyde M. Carpenter, JR., Mark A. Kwoka
  • Patent number: 8969137
    Abstract: Embodiments described herein relate to a method of manufacturing a packaged circuit having a solder flow-impeding plug on a lead frame. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch forming a trench. A non-conductive material that is adhesive to the lead frame is applied in the trench, such that the non-conductive material extends across the trench to form the solder flow-impeding plug. One or more components are attached to the internal surface of the lead frame and encapsulated. An external surface of the lead frame is etched at the dividing lines to disconnect different sections of lead frame as a second partial etch.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: March 3, 2015
    Assignee: Intersil Americas LLC
    Inventors: Randolph Cruz, Loyde M. Carpenter, Jr.
  • Patent number: 8877564
    Abstract: One embodiment is directed towards a method of manufacturing a packaged circuit. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch. One or more dies are attached to the internal surface of the lead frame and encapsulated. The method also includes partially etching an external surface of the lead frame at the dividing lines to disconnect different sections of lead frame as a second partial etch, wherein the second partial etch removes a laterally wider portion of the lead frame than the first partial etch of the internal surface; and partially etching the external surface of the lead frame as a third partial etch, wherein the third partial etch overlaps a portion of the second partial etch and extends deeper into the lead frame than the second partial etch.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: November 4, 2014
    Assignee: Intersil Americas LLC
    Inventors: Randolph Cruz, Loyde M. Carpenter, Jr.
  • Patent number: 8871572
    Abstract: Embodiments described herein relate to manufacturing a device. The method includes etching at least one recess pattern in an internal surface of a lead frame, the at least one recess pattern including a perimeter recess that defines a perimeter of a mounting area. The method also includes attaching a component to the internal surface of the lead frame such that a single terminal of the component is attached in the mounting area and the single terminal covers the perimeter recess, wherein the perimeter recess has a size and shape such that the recess is proximate a perimeter of the single terminal.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 28, 2014
    Assignee: Intersil Americas LLC
    Inventors: Randolph Cruz, Loyde M. Carpenter, Jr.
  • Publication number: 20140175627
    Abstract: Embodiments described herein relate to manufacturing a device. The method includes etching at least one recess pattern in an internal surface of a lead frame, the at least one recess pattern including a perimeter recess that defines a perimeter of a mounting area. The method also includes attaching a component to the internal surface of the lead frame such that a single terminal of the component is attached in the mounting area and the single terminal covers the perimeter recess, wherein the perimeter recess has a size and shape such that the recess is proximate a perimeter of the single terminal.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: INTERSIL AMERICAS LLC
    Inventors: Randolph Cruz, Loyde M. Carpenter, JR.
  • Publication number: 20140097529
    Abstract: Embodiments described herein relate to a method of manufacturing a packaged circuit having a solder flow-impeding plug on a lead frame. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch forming a trench. A non-conductive material that is adhesive to the lead frame is applied in the trench, such that the non-conductive material extends across the trench to form the solder flow-impeding plug. One or more components are attached to the internal surface of the lead frame and encapsulated. An external surface of the lead frame is etched at the dividing lines to disconnect different sections of lead frame as a second partial etch.
    Type: Application
    Filed: December 17, 2012
    Publication date: April 10, 2014
    Applicant: INTERSIL AMERICAS LLC
    Inventors: Randolph Cruz, Loyde M. Carpenter, JR.
  • Publication number: 20140001618
    Abstract: One embodiment is directed towards a method of manufacturing a packaged circuit. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch. One or more dies are attached to the internal surface of the lead frame and encapsulated. The method also includes partially etching an external surface of the lead frame at the dividing lines to disconnect different sections of lead frame as a second partial etch, wherein the second partial etch removes a laterally wider portion of the lead frame than the first partial etch of the internal surface; and partially etching the external surface of the lead frame as a third partial etch, wherein the third partial etch overlaps a portion of the second partial etch and extends deeper into the lead frame than the second partial etch.
    Type: Application
    Filed: September 27, 2012
    Publication date: January 2, 2014
    Applicant: INTERSIL AMERICAS LLC
    Inventors: Randolph Cruz, Loyde M. Carpenter, JR.
  • Publication number: 20130314879
    Abstract: A circuit module includes a plurality of electronic components and a single-layer conductive package substrate. The single-layer conductive package substrate is adapted to physically support and electrically interconnect the electronic components. The substrate has a peripheral portion and an interior portion. The peripheral portion includes a plurality of peripheral contact pads coupled to corresponding electronic components. The interior portion includes a plurality of floating contact pads that are electrically isolated from the peripheral contact pads and are coupled to corresponding electronic components.
    Type: Application
    Filed: June 28, 2012
    Publication date: November 28, 2013
    Applicant: INTERSIL AMERICAS LLC
    Inventors: Jian YIN, Nikhil KELKAR, Loyde M. CARPENTER, JR., Nattorn PONGRATANANUKUL, Patrick J. SELBY, Steven R. RIVET, Michael W. ALTHAR
  • Patent number: 8206836
    Abstract: A conductive clip having a riser or post formed along a side thereof includes a notch or opening formed in the riser or post to create a first riser or post section and second riser or post section separated by the notch or opening through which a tiebar extends. The conductive clip organization is will suited for formation as elongated strips of such conductive clips for automated machine assembly of the conductive clips in an integrated circuit package context.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: June 26, 2012
    Assignee: Intersil Americas, Inc.
    Inventors: Loyde M. Carpenter, Jr., Randolph Cruz, Nikhil Kelkar
  • Publication number: 20110033724
    Abstract: A conductive clip having a riser or post formed along a side thereof includes a notch or opening formed in the riser or post to create a first riser or post section and second riser or post section separated by the notch or opening through which a tiebar extends. The conductive clip organization is will suited for formation as elongated strips of such conductive clips for automated machine assembly of the conductive clips in an integrated circuit package context.
    Type: Application
    Filed: February 3, 2010
    Publication date: February 10, 2011
    Inventors: Loyde M. Carpenter, JR., Randolph Cruz, Nikhil Kelkar