Abstract: A computer-implemented method for managing information during a web conference is provided. The computer-implemented method includes collecting and formatting meeting application information at a processor of a computing device having a screen being shared with attendees of the web conference and collecting and formatting to-be-popup application information at the processor. The computer-implemented method further includes analyzing, by the processor, an urgency of the to-be-popup application information and a correlation between the to-be-popup application information and the meeting application information and determining, by the processor, whether to share the to-be-popup application information with a user of the computing device and with the attendees based on results of the analyzing.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: This application provides an epitaxial wafer processing method, the processing method comprises providing an epitaxial wafer; measuring the flatness of the epitaxial wafer; performing vapor phase etching for the epitaxial wafer not meet the standard; growing epitaxial layer on the epitaxial wafer after the vapor phase etching. Compared with the traditional polishing rework process, the vapor phase etching for the epitaxial wafer of this application is much simpler and faster, therefore it can improve the production yield.

Abstract: The present disclosure provides an annealing method for improving interface bonding strength of a wafer. The method includes: providing a substrate, the substrate having a bonding interface; performing a first annealing step, wherein the first annealing step is practiced in an oxygen-containing atmosphere, and an oxidation protection layer is formed on a surface of the substrate through the annealing step; and performing a second annealing step upon the first annealing step, wherein a temperature of the second annealing step is higher than that of the first annealing step, and the second annealing step is practiced in a nitrogen-free environment.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: A packaged light emitting device die 20 includes a package body having a profiled leadframe 10 embedded in a body 12 of reflecting material. The leadframe 10 is exposed on mounting surface 14 only on at least one solder bonding area 16. Solder 22 is present only on the at least one solder bonding area 16 and not elsewhere. The reflecting material provides the reflecting parts of the package so there is no need for a reflective layer to be deposited on leadframe 10. Moreover, the reflecting material can function as a solder resist to self-align the solder 22 to the at least one solder bonding area 16.

Abstract: A method for preparing a substrate with an insulating buried layer includes: providing a substrate, the substrate having a supporting layer and an insulating layer arranged on a surface of the supporting layer; performing first ion implantation, implanting modified ions into the substrate, wherein a distance from an interface between the insulating layer and the supporting layer to a Gaussian distribution peak of modified ion concentration is less than 50 nm, such that the modified ions form a nano cluster in the insulating layer; and performing a second ion implantation, continuing to implant the modified ions into the insulating layer, wherein the ions are implanted in the same way as the first ion implantation, and a distance from a Gaussian distribution peak of modified ion concentration in this step to the Gaussian distribution peak of modified ion concentration in the first ion implantation is less than 80 nm.

Abstract: The present disclosure provides a method for preparing a substrate with a carrier trapping center. The method includes: implanting bubbling ions into the semiconductor substrate to form a splitting layer, and implanting modified ions into the insulating layer to form a nano cluster; providing a supporting substrate; bonding the supporting substrate to the semiconductor substrate by using the insulating layer as an intermediate layer; performing a first heat treatment for the bonded substrate such that a splitting layer is formed at the position where the bubbling ions are implanted, and causing the semiconductor substrate to split at the position of the splitting layer; performing rapid thermal annealing for the substrate; and performing a second heat treatment for the rapidly thermally annealed semiconductor substrate to consolidate the bonding interface and form the nano cluster at the position where the modified ions are implanted.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: The present disclosure provides an annealing method for improving interface bonding strength of a wafer. The method includes: providing a substrate, the substrate having a bonding interface; performing a first annealing step, wherein the first annealing step is practiced in an oxygen-containing atmosphere, and an oxidation protection layer is formed on a surface of the substrate through the annealing step; and performing a second annealing step upon the first annealing step, wherein a temperature of the second annealing step is higher than that of the first annealing step, and the second annealing step is practiced in a nitrogen-free environment.

Abstract: A method for preparing a substrate with an insulating buried layer includes: providing a substrate, the substrate having a supporting layer and an insulating layer arranged on a surface of the supporting layer; performing first ion implantation, implanting modified ions into the substrate, wherein a distance from an interface between the insulating layer and the supporting layer to a Gaussian distribution peak of modified ion concentration is less than 50 nm, such that the modified ions form a nano cluster in the insulating layer; and performing a second ion implantation, continuing to implant the modified ions into the insulating layer, wherein the ions are implanted in the same way as the first ion implantation, and a distance from a Gaussian distribution peak of modified ion concentration in this step to the Gaussian distribution peak of modified ion concentration in the first ion implantation is less than 80 nm.

Abstract: The present disclosure provides a method for preparing a substrate with a carrier trapping center. The method includes: implanting bubbling ions into the semiconductor substrate to form a splitting layer, and implanting modified ions into the insulating layer to form a nano cluster; providing a supporting substrate; bonding the supporting substrate to the semiconductor substrate by using the insulating layer as an intermediate layer; performing a first heat treatment for the bonded substrate such that a splitting layer is formed at the position where the bubbling ions are implanted, and causing the semiconductor substrate to split at the position of the splitting layer; performing rapid thermal annealing for the substrate; and performing a second heat treatment for the rapidly thermally annealed semiconductor substrate to consolidate the bonding interface and form the nano cluster at the position where the modified ions are implanted.

Abstract: The present disclosure provides a method for preparing a substrate with a carrier trapping center. The method includes: injecting bubbling ions into the semiconductor substrate to form a splitting layer, and injecting modified ions into the insulating layer to form a nano cluster; providing a supporting substrate; bonding the supporting substrate to the semiconductor substrate by using the insulating layer as an intermediate layer; performing a first heat treatment for the bonded substrate such that a splitting layer is formed at the position where the bubbling ions are injected, and causing the semiconductor substrate to split at the position of the splitting layer; thinning a splitting surface of the split semiconductor substrate; and performing a second heat treatment for the thinned semiconductor substrate to consolidate the bonding interface and form the nano cluster at the position where the modified ions are injected.

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: A packaged light emitting device die 20 includes a package body having a profiled leadframe 10 embedded in a body 12 of reflecting material. The leadframe 10 is exposed on mounting surface 14 only on at least one solder bonding area 16. Solder 22 is present only on the at least one solder bonding area 16 and not elsewhere. The reflecting material provides the reflecting parts of the package so there is no need for a reflective layer to be deposited on leadframe 10. Moreover, the reflecting material can function as a solder resist to self-align the solder 22 to the at least one solder bonding area 16.

Abstract: A packaged light emitting device die includes a package body having a profiled leadframe embedded in a body of reflecting material. The leadframe is exposed on mounting surface only on at least one solder bonding area. Solder is present only on the at least one solder bonding area and not elsewhere. The reflecting material provides the reflecting parts of the package so there is no need for a reflective layer to be deposited on leadframe. Moreover, the reflecting material can function as a solder resist to self-align the solder to the at least one solder bonding area.

Abstract: A packaged light emitting device die includes a package body having a profiled leadframe embedded in a body of reflecting material. The leadframe is exposed on mounting surface only on at least one solder bonding area. Solder is present only on the at least one solder bonding area and not elsewhere. The reflecting material provides the reflecting parts of the package so there is no need for a reflective layer to be deposited on leadframe. Moreover, the reflecting material can function as a solder resist to self-align the solder to the at least one solder bonding area.

Abstract: This invention generally relates to a process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of the semiconductor silicon substrate with a gaseous acid in a reducing atmosphere at a temperature and duration sufficient to grow grown-in -defects disposed in the semiconductor silicon substrate to a size capable of being detected by an optical detection device.