Patents by Inventor Lu-Ming Lai

Lu-Ming Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220115425
    Abstract: An optical package structure and a method for manufacturing an optical package structure are provided. The optical package structure includes a sensor, an optical component and a fixing element. The optical component directly contacts the sensor. An interfacial area is defined by a contacting region of the optical component and the sensor. The fixing element is disposed outside of the interfacial area for bonding the optical component and the sensor.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 14, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Ling HUANG, Lu-Ming LAI, Ying-Chung CHEN
  • Patent number: 11296651
    Abstract: A semiconductor package structure includes an organic substrate having a first surface, a first recess depressed from the first surface, a first chip over the first surface and covering the first recess, thereby defining a first cavity enclosed by a back surface of the first chip and the first recess, and a second chip over the first chip. The first cavity is an air cavity or a vacuum cavity.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Ching-Han Huang, Hui-Chung Liu, Kuo-Hua Lai, Cheng-Ling Huang
  • Patent number: 11276806
    Abstract: A semiconductor device package includes a carrier, a die, an encapsulation layer and a thickness controlling component. The die is disposed on the carrier, wherein the die includes a first surface. The encapsulation layer is disposed on the carrier, and encapsulates a portion of the first surface of the die. The encapsulation layer defines a space exposing another portion of the first surface of the die. The thickness controlling component is disposed in the space.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi Wen Chiang, Kuang-Hsiung Chen, Lu-Ming Lai, Hsun-Wei Chan, Hsin-Ying Ho, Shih-Chieh Tang
  • Patent number: 11276797
    Abstract: An optical module and a method of manufacturing an optical module are provided. The optical module includes a carrier, an electronic component, a lid, a diffuser and a bonding layer. The electronic component is disposed on the carrier. The lid is disposed on the carrier. The lid has a first cavity to accommodate the electronic component. The lid defines a first aperture over the first cavity. The diffuser is disposed within the first aperture. The bonding layer is disposed between the diffuser and a sidewall of the first aperture.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiang-Cheng Tsai, Lu-Ming Lai, Hsun-Wei Chan, Ying-Chung Chen
  • Patent number: 11276720
    Abstract: An optical package includes a substrate, an image sensor, a microlens, an optical filter layer, a constraining layer, and a buffer layer. The image sensor is disposed on the substrate. The microlens having a first Young's modulus is disposed on the image sensor. The optical filter layer having a second Young's modulus disposed on the microlens. The constraining layer is disposed between the optical filter layer and the microlens. The buffer layer having a third Young's modulus disposed on the constraining layer. The third Young's modulus is greater than the first Young's modulus and smaller than the second Young's modulus.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shih-Chieh Tang, Lu-Ming Lai, Chia Yun Hsu
  • Publication number: 20220068747
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a semiconductor package device, a first constraint structure and a second constraint structure. The first constraint structure is connected to the semiconductor package device. The second constraint structure is connected to the semiconductor package device and under a projection of the semiconductor package device.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Che HUANG, Lu-Ming LAI, Ying-Chung CHEN
  • Patent number: 11262197
    Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: March 1, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ying-Chung Chen, Hsun-Wei Chan, Lu-Ming Lai, Kuang-Hsiung Chen
  • Patent number: 11217499
    Abstract: A semiconductor package structure includes a substrate; a first die on the substrate, wherein an active surface of the first die is facing away from the substrate; a second die on the active surface of the first die, electrically connected to the first die through a plurality of conductive terminals; and a sealing structure on the active surface of the first die, surrounding the plurality of conductive terminals and abutting the second die thereby forming a cavity between the first die and the second die. A method for manufacturing the semiconductor package structure is also provided.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: January 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Hui-Chung Liu
  • Patent number: 11211536
    Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: December 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Yi Wu, Lu-Ming Lai, Yu-Ying Lee, Yung-Yi Chang
  • Publication number: 20210358823
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a semiconductor package structure includes a semiconductor die and a light absorbing layer. The semiconductor die has a first surface, a second surface and a third surface. An active layer of the semiconductor die is adjacent to the first surface. The second surface is opposite to the first surface. The third surface extends from the first surface to the second surface. The light absorbing layer covers the second surface and the third surface of the semiconductor die. The semiconductor die has a thickness defined from the first surface to the second surface, and the thickness of the semiconductor die is less than or equal to about 300 micrometers (?m).
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Lu-Ming LAI, Yu-Che HUANG, Shih-Chieh TANG, Yu-Min PENG, Hui-Chung LIU
  • Patent number: 11174157
    Abstract: A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: November 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Yu-Hsuan Tsai, Yin-Hao Chen, Hsin Lin Wu, San-Kuei Yu
  • Publication number: 20210280755
    Abstract: A semiconductor device package includes a light-emitting device, a diffuser structure, a first optical sensor, and a second optical sensor. The light-emitting device has a light-emitting surface. The diffuser structure is above the light-emitting surface of the light-emitting device. The first optical sensor is disposed below the diffuser structure, and the first optical sensor is configured to detect a first reflected light reflected by the diffuser structure. The second optical sensor is disposed below the diffuser structure, and the second optical sensor is configured to detect a second reflected light reflected by the diffuser structure.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsin-Ying HO, Hsun-Wei CHAN, Shih-Chieh TANG, Lu-Ming LAI
  • Publication number: 20210276860
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate with a first groove and a semiconductor device. The first groove has a first portion, a second portion, and a third portion, and the second portion is between the first portion and the third portion. The semiconductor device includes a membrane and is disposed on the second portion of the first groove. The semiconductor device has a first surface adjacent to the substrate and opposite to the membrane. The membrane is exposed by the first surface.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 9, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Liang HSIAO, Lu-Ming LAI, Ching-Han HUANG, Chia-Hung SHEN
  • Publication number: 20210257988
    Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component and a support component. The first electronic component is disposed on the substrate. The first electronic component has a backside surface facing a first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The backside surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.
    Type: Application
    Filed: February 18, 2020
    Publication date: August 19, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Lu-Ming LAI, Ching-Han HUANG, Kuo-Hua LAI, Hui-Chung LIU
  • Patent number: 11091365
    Abstract: The present disclosure provides a package structure and a manufacturing method. The package structure includes a substrate, a cover, a conductive pattern, and a sensing component. The cover is disposed on the substrate. The cover and the substrate define an accommodation space. The conductive pattern includes a conductive line. The conductive line is disposed on an internal surface of the cover exposed by the accommodation space, and is electrically connected to the substrate. The sensing component is disposed on the internal surface of the cover, and is electrically connected to the conductive line.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: August 17, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ching-Han Huang, Lu-Ming Lai
  • Patent number: 11088054
    Abstract: A lead frame includes a die pad having a pad top surface and a pad bottom surface opposite to the top pad surface, a plurality of leads, each having a top lead surface and a bottom lead surface opposite to the top lead surface and disposed around the die pad, and a first molding compound disposed between the die pad and each of the leads. The first molding compound exposes the top pad surface of the die pad by covering a portion of the periphery of the top pad surface of the die pad. A method for manufacturing the lead frame is also disclosed.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 10, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Ying-Chung Chen, Hui-Chung Liu
  • Patent number: 11081413
    Abstract: A semiconductor package structure includes a substrate, a semiconductor die, a lid and a cap. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate. The cap is disposed on the lid. The substrate, the lid and the cap define a cavity in which the semiconductor die is disposed, and a pressure in the cavity is greater than an atmospheric pressure outside the cavity.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 3, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsin Lin Wu, Yu-Hsuan Tsai, Chang Chin Tsai, Lu-Ming Lai, Ching-Han Huang
  • Publication number: 20210210662
    Abstract: A semiconductor device package includes a carrier, a die, an encapsulation layer and a thickness controlling component. The die is disposed on the carrier, wherein the die includes a first surface. The encapsulation layer is disposed on the carrier, and encapsulates a portion of the first surface of the die. The encapsulation layer defines a space exposing another portion of the first surface of the die. The thickness controlling component is disposed in the space.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yi Wen CHIANG, Kuang-Hsiung CHEN, Lu-Ming LAI, Hsun-Wei CHAN, Hsin-Ying HO, Shih-Chieh TANG
  • Publication number: 20210206628
    Abstract: A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 8, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Hsuan TSAI, Lu-Ming LAI, Chien-Wei FANG, Ching-Han HUANG
  • Publication number: 20210183839
    Abstract: An optical module includes a carrier, a light emitter disposed on the carrier, a light detector disposed on the carrier, and a housing disposed on the carrier. The housing defines a first opening that exposes the light emitter and a second opening that exposes the light detector. The optical module further includes a first light transmission element disposed on the first opening and a second light transmission element disposed on the second opening. A first opaque layer is disposed on the first light transmission element, the first opaque layer defining a first aperture, and a second opaque layer disposed on the second light transmission element, the second opaque layer defining a second aperture.
    Type: Application
    Filed: February 26, 2021
    Publication date: June 17, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsin-Ying HO, Ying-Chung CHEN, Lu-Ming LAI