Patents by Inventor Lu-Shan Chiang

Lu-Shan Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7696884
    Abstract: An RFID system comprises an intermediate device that includes a first and second antenna coils connected together in a close loop format. The coils are formed on a flexible substrate that can be folded around a magnetic flux blocker such that one loop is on side of the blocker and the other loop is on the other side of the blocker. The intermediate device can then improve communication between a reader on one side of the blocker and a tag on the other. The coil on the reader side of the blocker can receive RF signals being generated by the reader and convert them to an electrical signal that can be passed to the coil on the tag side of the blockage. The second coil can then generate an RF signal that can be transmitted to the tag.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: April 13, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Huan-Chin Luo, Lu-Shan Chiang, Ying-Che Lo, Chia-Jui Shen, Po-Chih Lai, Kung-Hua Lee
  • Publication number: 20070222602
    Abstract: An RFID system comprises an intermediate device that includes a first and second antenna coils connected together in a close loop format. The coils are formed on a flexible substrate that can be folded around a magnetic flux blocker such that one loop is on side of the blocker and the other loop is on the other side of the blocker. The intermediate device can then improve communication between a reader on one side of the blocker and a tag on the other. The coil on the reader side of the blocker can receive RF signals being generated by the reader and convert them to an electrical signal that can be passed to the coil on the tag side of the blockage. The second coil can then generate an RF signal that can be transmitted to the tag.
    Type: Application
    Filed: March 17, 2006
    Publication date: September 27, 2007
    Inventors: Huan-Chin Luo, Lu-Shan Chiang, Ying-Che Lo, Chia-Jui Shen, Po-Chih Lai, Kung-Hua Lee
  • Publication number: 20040209391
    Abstract: A method of forming a MEM device with an integrated circuit that includes providing a semiconductor substrate including a first region and a second region, forming an integrated circuit device on the first region, forming a first insulating layer on the semiconductor substrate, etching the first insulating layer to form a first dielectric layer on the first region and a second dielectric layer on the second region spaced apart from the first dielectric layer, forming a second insulating layer over the semiconductor substrate, the first dielectric layer and the second dielectric layer, etching the second insulating layer to expose the first dielectric layer, forming a third insulating layer over the semiconductor substrate, the second insulating layer and the first dielectric layer, etching the third insulating layer to form a plurality of vias, and forming a metal layer over the semiconductor substrate to fill the vias.
    Type: Application
    Filed: April 18, 2003
    Publication date: October 21, 2004
    Applicant: Macronix International Co., Ltd.
    Inventors: Shuo-Lun Tu, Lu-Shan Chiang
  • Patent number: 6797534
    Abstract: A method of forming a MEM device with an integrated circuit that includes providing a semiconductor substrate including a first region and a second region, forming an integrated circuit device on the first region, forming a first insulating layer on the semiconductor substrate, etching the first insulating layer to form a first dielectric layer on the first region and a second dielectric layer on the second region spaced apart from the first dielectric layer, forming a second insulating layer over the semiconductor substrate, the first dielectric layer and the second dielectric layer, etching the second insulating layer to expose the first dielectric layer, forming a third insulating layer over the semiconductor substrate, the second insulatng layer and the first dielectric layer, etching the third insulating layer to form a plurality of vias, and forming a metal layer over the semiconductor substrate to fill the vias.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: September 28, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Shuo-Lin Tu, Lu-Shan Chiang, Shih-Lin Chu