Patents by Inventor Luca Bert

Luca Bert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220398045
    Abstract: A memory device comprises a file system and a processing device to perform operations comprising receiving, from the file system, a first data access command comprising a payload, responsive to receiving the first data access command, determining, using the file system, a characteristic of the payload, wherein the characteristic of the payload indicates whether the first data access command is for data or for metadata, and sending a second data access command to a memory sub-system, wherein the second data access command includes an indication of a memory region of a memory device in which the memory sub-system is to store the payload, wherein the indication of the memory region is based on the characteristic of the payload.
    Type: Application
    Filed: August 22, 2022
    Publication date: December 15, 2022
    Inventor: Luca Bert
  • Patent number: 11520656
    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a plurality of memory devices of the set, wherein the failure causes data of the plurality of memory devices to be inaccessible; determining the capacity of the set of memory devices has changed to a reduced capacity; notifying a host system of the reduced capacity, wherein the notifying indicates a set of storage units comprising the data that is inaccessible; recovering the data of the set of storage units from the host system after the failure; and updating the set of memory devices to store the recovered data and to change the capacity to the reduced capacity.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 6, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 11520500
    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a memory device of the set, wherein the memory device stores multiple bits per memory cell; sending a message to a host system indicating a reduced capacity of the set of memory devices; receiving from the host system a message to continue at the reduced capacity; and updating the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 6, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Publication number: 20220350759
    Abstract: A system includes a first memory device including a non-volatile memory device, a second memory device and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including configuring a system in accordance with a configuration designating an interface standard for exposing a storage element implemented on the first memory device to a first protocol of the interface standard and a persistent memory region (PMR) implemented on the second memory device to a second protocol of the interface standard, and performing at least one system operation based on the configuration.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Joseph H. Steinmetz, Luca Bert, William Akin
  • Publication number: 20220334759
    Abstract: Data from a host system is received at a memory device, where the memory device includes a primary region to initially store the data received from the host system and one or more secondary regions to store data transferred from the primary region. A write operation is performed on one or more write units of the primary region with the data received from the host system, where a write unit of the primary region has lower density blocks than a write unit of the secondary region. Whether a subset of write units of the primary region corresponding to a pre-determined number of write units is written with at least a portion of the data received from the host system is determined. In response to determining that the subset of write units of the primary region is written, another write operation is performed on at least one write units of the secondary region with respective data of the subset of write units of the primary region.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Abdelhakim Alhussien, Ayberk Ozturk, Karl D. Schuh, Luca Bert
  • Publication number: 20220334740
    Abstract: A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.
    Type: Application
    Filed: April 16, 2021
    Publication date: October 20, 2022
    Inventors: Joseph H. Steinmetz, Luca Bert, William Akin
  • Publication number: 20220308780
    Abstract: A memory sub-system can determine a block granularity for an input/output (I/O) data stream received from a host system. The memory sub-system can determine that the block granularity is different than a memory block granularity of a first memory region in a first namespace of the one or more memory devices, where the first memory region is to store the I/O data stream. The memory sub-system can accumulate blocks from the I/O data stream in a second memory region in a second namespace of the one or more memory devices. Responsive to a capacity of the accumulated blocks in the second memory region satisfying a threshold criterion, the memory sub-system can migrate the accumulated plurality of blocks from the second memory region to the first memory region.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 29, 2022
    Inventors: Kumar VKH Kanteti, Luca Bert
  • Publication number: 20220300175
    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a host system: receiving, by a host system, an indication that a storage capacity of a memory sub-system is affected by a failure, wherein the memory sub-system stores data of a storage structure and comprises memory cells storing multiple bits per cell; instructing, by the host system, the memory sub-system to operate at a reduced capacity, wherein the reduced capacity reduces the quantity of bits stored per memory cell; receiving, by the host system, an indication that the memory sub-system comprises data in excess of the reduced capacity; providing, by the host system, a storage location to the memory sub-system, wherein the storage location is external to the memory sub-system; and enabling the memory sub-system to store the data of the storage structure at the storage location.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventor: Luca Bert
  • Publication number: 20220300174
    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a memory device of the set, wherein the memory device stores multiple bits per memory cell; sending a message to a host system indicating a reduced capacity of the set of memory devices; receiving from the host system a message to continue at the reduced capacity; and updating the set of memory devices based on the reduced capacity, wherein the updating comprises reducing a quantity of bits stored per memory cell of the memory device.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventor: Luca Bert
  • Publication number: 20220300372
    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of a plurality of memory devices of the set, wherein the failure causes data of the plurality of memory devices to be inaccessible; determining the capacity of the set of memory devices has changed to a reduced capacity; notifying a host system of the reduced capacity, wherein the notifying indicates a set of storage units comprising the data that is inaccessible; recovering the data of the set of storage units from the host system after the failure; and updating the set of memory devices to store the recovered data and to change the capacity to the reduced capacity.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventor: Luca Bert
  • Publication number: 20220300376
    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a memory sub-system: detecting a failure of at least one memory device of the set, wherein the failure affects stored data; notifying a host system of a change in a capacity of the set of memory devices; receiving from the host system an indication to continue at a reduced capacity; and updating the set of memory devices to change the capacity to the reduced capacity.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventor: Luca Bert
  • Publication number: 20220300377
    Abstract: A system and method for managing a reduction in capacity of a memory sub-system. An example method involving a host system: determining, by a host system, that a failure affects a storage capacity of a memory sub-system, wherein the memory sub-system comprises stored data of a storage structure; instructing, by the host system, the memory sub-system to operate at a reduced capacity and to retain the stored data of the storage structure; receiving, by the host system, a set of storage units of the memory sub-system that are affected by the failure; and recovering, by the host system, data that was in the set of storage units affected by the failure.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventor: Luca Bert
  • Publication number: 20220300195
    Abstract: Host data associated with a first region of a memory device is identified. The host data is stored in a buffer, and the first region of the memory device is designated as open. The host data is padded to a predetermined size and written to the first region of the memory device. A context associated with the first region of the memory device is updated. The first region of the memory device is designated as closed.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 22, 2022
    Inventor: Luca Bert
  • Publication number: 20220276887
    Abstract: A processing device, operatively coupled with a memory component, is configured to provide a plurality of virtual memory controllers and to provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The processing device further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, wherein each of the plurality of physical functions corresponds to a different virtual machine running on the host computing system, and manages input/output (IO) operations received from the host computing systems and directed to the plurality of physical functions, as well as background operations performed on the memory component, in view of class of service parameters associated with the plurality of physical functions.
    Type: Application
    Filed: May 11, 2022
    Publication date: September 1, 2022
    Inventor: Luca Bert
  • Publication number: 20220276789
    Abstract: An input/output (I/O) write request directed at a plurality of memory devices having memory cells is received by a processing device. The write request includes a set of data. The processing device appends the set of data to a compound data object. The compound data object comprises one or more sequentially written data objects. The processing device associates the compound data object with one or more groups of memory cells of the plurality of memory devices. The processing device causes the compound data object to be written to the one or more groups of memory cells of the plurality of memory devices.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventor: Luca Bert
  • Patent number: 11429544
    Abstract: A host command is received to configure a system to have a configuration designating an interface standard for exposing a storage element and a persistent memory region (PMR). The storage element is visible to a first protocol of the interface standard and the PMR is visible to a second protocol of the interface standard. The storage element is implemented on a first memory device of the system including a non-volatile memory device and the PMR is implemented on a second memory device of the system. The system is configured in accordance with the configuration.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Joseph H. Steinmetz, Luca Bert, William Akin
  • Patent number: 11422745
    Abstract: A memory device comprises a first region configured as non-zoned addressable memory and a second region configured as a zone namespace. A write command comprising a payload and a functional designation of the payload is received, wherein the functional description indicates whether the payload comprises sequentially-writable data. Based on the functional designation of the payload, a corresponding one of the first region or the second region of the memory device is determined, wherein the second region is to store sequentially-writable data. The payload is stored in the corresponding one of the first region or the second region of the memory device.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: August 23, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 11403032
    Abstract: Data from a host system is received at a memory device, where the memory device includes a primary region to initially store the data received from the host system and one or more secondary regions to store data transferred from the primary region. A write operation is performed on one or more write units of the primary region with the data received from the host system, where a write unit of the primary region has lower density blocks than a write unit of the secondary region. Whether a subset of write units of the primary region corresponding to a pre-determined number of write units is written with at least a portion of the data received from the host system is determined. In response to determining that the subset of write units of the primary region is written, another write operation is performed on at least one write units of the secondary region with respective data of the subset of write units of the primary region.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Abdelhakim Alhussien, Ayberk Ozturk, Karl D. Schuh, Luca Bert
  • Publication number: 20220197556
    Abstract: A host command is received to configure a system to have a configuration designating a first interface standard at a first port for exposing a storage element and a second interface standard at a second port for exposing a persistent memory region (PMR). The storage element is implemented on a first memory device of the system and the PMR is implemented on a second memory device of the system. The second interface standard implements one or more alternate protocols supported by the first interface standard. The system is configured in accordance with the configuration.
    Type: Application
    Filed: January 13, 2021
    Publication date: June 23, 2022
    Inventors: Luca Bert, Joseph H. Steinmetz
  • Publication number: 20220197833
    Abstract: A host command is received to configure a system to have a configuration designating an interface standard for exposing a storage element and a persistent memory region (PMR). The storage element is visible to a first protocol of the interface standard and the PMR is visible to a second protocol of the interface standard. The storage element is implemented on a first memory device of the system including a non-volatile memory device and the PMR is implemented on a second memory device of the system. The system is configured in accordance with the configuration.
    Type: Application
    Filed: January 27, 2021
    Publication date: June 23, 2022
    Inventors: Joseph H. Steinmetz, Luca Bert, William Akin