Patents by Inventor Luca Fasoli
Luca Fasoli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9245629Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.Type: GrantFiled: October 18, 2013Date of Patent: January 26, 2016Assignee: SANDISK 3D LLCInventors: George Samachisa, Luca Fasoli, Masaaki Higashitani, Roy Edwin Scheuerlein
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Patent number: 9105576Abstract: In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.Type: GrantFiled: August 11, 2014Date of Patent: August 11, 2015Assignee: SanDisk 3D LLCInventors: Yung-Tin Chen, Andrei Mihnea, Roy E. Scheuerlein, Luca Fasoli
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Patent number: 8982597Abstract: The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.Type: GrantFiled: January 31, 2012Date of Patent: March 17, 2015Assignee: Sandisk 3D LLCInventors: Tianhong Yan, Luca Fasoli
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Patent number: 8913413Abstract: The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.Type: GrantFiled: January 31, 2012Date of Patent: December 16, 2014Assignee: SanDisk 3D LLCInventors: Tianhong Yan, Luca Fasoli
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Publication number: 20140346433Abstract: In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.Type: ApplicationFiled: August 11, 2014Publication date: November 27, 2014Inventors: Yung-Tin Chen, Andrei Mihnea, Roy E. Scheuerlein, Luca Fasoli
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Patent number: 8841648Abstract: In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.Type: GrantFiled: October 14, 2010Date of Patent: September 23, 2014Assignee: SanDisk 3D LLCInventors: Yung-Tin Chen, Andrei Mihnea, Roy E. Scheuerlein, Luca Fasoli
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Patent number: 8824191Abstract: A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.Type: GrantFiled: August 22, 2013Date of Patent: September 2, 2014Assignee: Sandisk 3D LLCInventors: George Samachisa, Luca Fasoli, Yan Li, Tianhong Yan
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Patent number: 8780651Abstract: A system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete.Type: GrantFiled: June 28, 2012Date of Patent: July 15, 2014Assignee: SanDisk 3D LLCInventors: Tianhong Yan, Luca Fasoli
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Patent number: 8711596Abstract: A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.Type: GrantFiled: August 31, 2012Date of Patent: April 29, 2014Assignee: Sandisk 3D LLCInventors: Tianhong Yan, Luca Fasoli
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Publication number: 20140043911Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.Type: ApplicationFiled: October 18, 2013Publication date: February 13, 2014Applicant: SANDISK 3D LLCInventors: George Samachisa, Luca Fasoli, Masaaki Higashitani, Roy Edwin Scheuerlein
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Patent number: 8638586Abstract: A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.Type: GrantFiled: May 23, 2012Date of Patent: January 28, 2014Assignee: Sandisk 3D LLCInventors: Tianhong Yan, Luca Fasoli
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Publication number: 20140022848Abstract: A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.Type: ApplicationFiled: August 22, 2013Publication date: January 23, 2014Applicant: SANDISK 3D LLCInventors: George Samachisa, Luca Fasoli, Yan Li, Tianhong Yan
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Patent number: 8547720Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.Type: GrantFiled: June 1, 2011Date of Patent: October 1, 2013Assignee: Sandisk 3D LLCInventors: George Samachisa, Luca Fasoli, Masaaki Higashitani, Roy Edwin Scheuerlein
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Patent number: 8526237Abstract: A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.Type: GrantFiled: June 1, 2011Date of Patent: September 3, 2013Assignee: SanDisk 3D LLCInventors: George Samachisa, Luca Fasoli, Yan Li, Tianhong Yan
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Patent number: 8427890Abstract: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.Type: GrantFiled: June 5, 2012Date of Patent: April 23, 2013Assignee: SanDisk 3D LLCInventors: Gopinath Balakrishnan, Luca Fasoli, Tz-Yi Liu, Yuheng Zhang, Yan Li
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Patent number: 8397024Abstract: A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.Type: GrantFiled: March 31, 2009Date of Patent: March 12, 2013Assignee: SanDisk 3D LLCInventors: Luca Fasoli, Yuheng Zhang, Gopinath Balakrishnan
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Patent number: 8395948Abstract: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.Type: GrantFiled: June 5, 2012Date of Patent: March 12, 2013Assignee: SanDisk 3D LLCInventors: Gopinath Balakrishnan, Luca Fasoli, Tz-Yi Liu, Yuheng Zhang, Yan Li
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Patent number: 8358528Abstract: A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay.Type: GrantFiled: April 4, 2011Date of Patent: January 22, 2013Assignee: SanDisk 3D, LLCInventors: Tianhong Yan, Luca Fasoli
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Patent number: RE46154Abstract: A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.Type: GrantFiled: May 23, 2014Date of Patent: September 20, 2016Assignee: SanDisk Technologies LLCInventors: Luca Fasoli, Yuheng Zhang, Gopinath Balakrishnan
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Patent number: RE46348Abstract: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.Type: GrantFiled: March 31, 2014Date of Patent: March 21, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Gopinath Balakrishnan, Luca Fasoli, Tz-Yi Liu, Yuheng Zhang, Yan Li