Patents by Inventor Lucian A. D'Asaro

Lucian A. D'Asaro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5578162
    Abstract: An integrated semiconductor device is formed by bonding the conductors of one fabricated semiconductor device having a substrate to the conductors on another fabricated semiconductor device having a substrate, flowing an etch-resist in the form of an uncured cement (e.g. epoxy) between the devices, allowing the etch-resist to solidify, and removing the substrate from one of the semiconductor devices. Preferably the etch-resist epoxy is retained to impart mechanical strength to the device. More specifically, a hybrid semiconductor device is formed by bonding the conductors of one or more GaAs/AlGaAs multiple quantum well modulators to conductors on an IC chip, wicking an uncured epoxy between the modulators and the chip, allowing the epoxy to cure, and removing the substrate from the modulator.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: November 26, 1996
    Assignee: Lucent Technologies Inc.
    Inventors: Lucian A. D'Asaro, Donald W. Dahringer, Keith W. Goossen, James A. Walker
  • Patent number: 5298454
    Abstract: Applicants have discovered a method of reproducibly fabricating SEED devices having an enhanced contrast ratio by adjusting the thickness of a cap layer in relation to the reflector stacks to form a Fabry-Perot cavity. Specifically, after growth of the reflector stack and the quantum wells, the optical thickness of the region above reflector stacks is measured without breaking vacuum, and based on such measurement a cap layer is grown of sufficient thickness to form a Fabry-Perot cavity for light of desired wavelength. The result is a device with enhanced contrast between the "on" and "off" states sufficiently so that the state can be directly read without differential processing.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: March 29, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Lucian A. D'Asaro, Jenn-Ming Kuo, Shin-Shem Pei
  • Patent number: 5289015
    Abstract: FETs and quantum well diodes are combined on the same semi-insulating substrate, while providing the FETs with protection from spurious voltages. A deeply buried P region in the semi-insulating substrate is partitioned by a high resistivity proton implanted region, to provide both the P region of the quantum well diode and an isolating buried P layer for the FETs.
    Type: Grant
    Filed: October 31, 1991
    Date of Patent: February 22, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Leo M. F. Chirovsky, Lucian A. D'Asaro, Shin-Shem Pei, Ted K. Woodward
  • Patent number: 5056098
    Abstract: A light emitting device uses a vertical cavity surface emitting laser having a voltage controlled mirror which is used, for example, to turn the laser ON and OFF by varying the reflectivity of one mirror forming the laser cavity.
    Type: Grant
    Filed: July 5, 1990
    Date of Patent: October 8, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: Philip J. Anthony, Leo M. F. Chirovsky, Lucian A. D'Asaro, Vincent D. Mattera, Robert A. Morgan
  • Patent number: 4569718
    Abstract: The use of an anisotropic etchant containing BCl.sub.3 and a source of atomic chlorine for III-V semiconductor materials has yielded improved results for semiconductor devices. For example, via gallium arsenide field effect transistors produced using this anisotropic etchant to fabricate via holes exhibit excellent electrical characteristics.
    Type: Grant
    Filed: September 14, 1984
    Date of Patent: February 11, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: Alexander D. Butherus, Lucian A. D'Asaro
  • Patent number: 4403241
    Abstract: The use of an anisotropic etchant containing BCl.sub.3 and a source of atomic chlorine for III-V semiconductor materials has yielded improved results for semiconductor devices. For example, via gallium arsenide field effect transistors produced using this anisotropic etchant to fabricate via holes exhibit excellent electrical characteristics.
    Type: Grant
    Filed: August 22, 1980
    Date of Patent: September 6, 1983
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Alexander D. Butherus, Lucian A. D'Asaro
  • Patent number: 4399004
    Abstract: A process is described for plating gold on metal surfaces electrically attached to a compound semiconductor. The procedure is particularly valuable where gold is to be in small holes or crevices in semiconductor structure since electroplating on the semiconductor surface is avoided. The process is useful for providing low inductance electrical connection to various parts of semiconductor devices such as to the source in gallium arsenide field-effect transistors.
    Type: Grant
    Filed: June 11, 1981
    Date of Patent: August 16, 1983
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Reginald R. Buckley, Lucian A. D'Asaro, Paul A. Kohl, Frederick W. Ostermayer, Jr., Catherine Wolowodiuk
  • Patent number: 4244775
    Abstract: A method for thinning and polishing semiconductor materials such as gallium arsenide is disclosed. This method utilizes a chemical etchant in conjunction with a grooved flat polishing plate. The polishing plate has a hardness greater than 2 on the mohs scale. High quality polished surfaces are obtained. Exemplary of polishing plate materials is quartz.
    Type: Grant
    Filed: April 30, 1979
    Date of Patent: January 13, 1981
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Lucian A. D'Asaro
  • Patent number: 4162337
    Abstract: A process is described for making III-V semiconductor devices with electroless gold plated layers. Various III-V semiconductors are used, particularly those containing gallium, aluminum and indium such as GaAs, Al.sub.x Ga.sub.1-x As, GaP, Al.sub.x Ga.sub.1-x P.sub.y As.sub.1-y, In.sub.x Ga.sub.1-x P.sub.y As.sub.1-y and InP. This process involves activation of a semiconductor surface and then electrolessly gold plating the surface. Electroless gold films produced in accordance with this process have good adherence to the semiconductor surface and are useful not only for electrical connection to the semiconductor, but also for attachment to headers for mechanical convenience and to maintain temperature stability. Exemplary devices are field effect transistors, particularly those operating in the microwave region, and semiconductor lasers.
    Type: Grant
    Filed: November 14, 1977
    Date of Patent: July 24, 1979
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Lucian A. D'Asaro, Yutaka Okinaka