Abstract: Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of different floorplans are executed using the circuit architecture in the IC. The plurality of PPG circuit blocks mimic the memory access patterns of the kernels for each of the plurality of different floorplans during the executing. One or more design constraints are generated based on a selected floorplan. The selected floorplan is selected from the plurality of different floorplans based on one or more performance metrics determined from the executing.

Abstract: Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of different floorplans are executed using the circuit architecture in the IC. The plurality of PPG circuit blocks mimic the memory access patterns of the kernels for each of the plurality of different floorplans during the executing. One or more design constraints are generated based on a selected floorplan. The selected floorplan is selected from the plurality of different floorplans based on one or more performance metrics determined from the executing.

Abstract: Methods, systems, and computer readable media for automatically generating a fuzzer for testing a network device using the fuzzer are disclosed. According to one method, a functional description of a network communications protocol finite state machine is received as input. Operation of the protocol is simulated using the functional description of the network communications protocol finite state machine to generate a set of valid conversations in the protocol. A fuzzer is generated from the set of valid conversations. The fuzzer is used to send messages to test a device under test. Responses to the device under test to the messages generated by the fuzzer are analyzed.

Abstract: Methods, systems, and computer readable media for automatically generating a fuzzer for testing a network device using the fuzzer are disclosed. According to one method, a functional description of a network communications protocol finite state machine is received as input. Operation of the protocol is simulated using the functional description of the network communications protocol finite state machine to generate a set of valid conversations in the protocol. A fuzzer is generated from the set of valid conversations. The fuzzer is used to send messages to test a device under test. Responses to the device under test to the messages generated by the fuzzer are analyzyed.