Patents by Inventor Luciano Mule'Stagno

Luciano Mule'Stagno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7201800
    Abstract: A process for imparting controlled oxygen precipitation behavior to a single crystal silicon wafer. Specifically, prior to formation of the oxygen precipitates, the wafer bulk comprises dopant stabilized oxygen precipitate nucleation centers. The dopant is selected from a group consisting of nitrogen and carbon, and the concentration of the dopant is sufficient to allow the oxygen precipitate nucleation centers to withstand thermal processing, such as an epitaxial deposition process, while maintaining the ability to dissolve any grown-in nucleation centers.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: April 10, 2007
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Jeffrey L. Libbert, Richard J. Phillips, Milind Kulkarni, Mohsen Banan, Stephen J. Brunkhorst
  • Patent number: 7097718
    Abstract: Epitaxial wafers comprising a single crystal silicon substrate comprising agglomerated vacancy defects and having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated intrinsic point defects on the substrate surface upon which the epitaxial layer is deposited.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: August 29, 2006
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
  • Publication number: 20050048247
    Abstract: A process for imparting controlled oxygen precipitation behavior to a single crystal silicon wafer. Specifically, prior to formation of the oxygen precipitates, the wafer bulk comprises dopant stabilized oxygen precipitate nucleation centers. The dopant is selected from a group consisting of nitrogen and carbon, and the concentration of the dopant is sufficient to allow the oxygen precipitate nucleation centers to withstand thermal processing, such as an epitaxial deposition process, while maintaining the ability to dissolve any grown-in nucleation centers.
    Type: Application
    Filed: October 12, 2004
    Publication date: March 3, 2005
    Inventors: Luciano Mule'Stagno, Jeffrey Libbert, Richard Phillips, Milind Kulkarni, Mohsen Banan, Stephen Brunkhorst
  • Patent number: 6808781
    Abstract: A silicon wafer having a controlled oxygen precipitation behavior such that a denuded zone extending inward from the front surface and oxygen precipitates in the wafer bulk sufficient for intrinsic gettering purposes are ultimately formed. Specifically, prior to formation of the oxygen precipitates, the wafer bulk comprises dopant stabilized oxygen precipitate nucleation centers. The dopant is selected from a group consisting of nitrogen and carbon and the concentration of the dopant is sufficient to allow the oxygen precipitate nucleation centers to withstand thermal processing such as an epitaxial deposition process while maintaining the ability to dissolve any grown-in nucleation centers.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: October 26, 2004
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Jeffrey L. Libbert, Richard J. Phillips, Milind Kulkarni, Mohsen Banan, Stephen J. Brunkhorst
  • Publication number: 20030205191
    Abstract: Epitaxial wafers comprising a single crystal silicon substrate comprising agglomerated vacancy defects and having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated intrinsic point defects on the substrate surface upon which the epitaxial layer is deposited.
    Type: Application
    Filed: May 20, 2003
    Publication date: November 6, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule ' Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
  • Patent number: 6638357
    Abstract: A method for revealing agglomerated intrinsic point defect. The method comprising coating a sample with a metal capable of decorating agglomerated intrinsic point defects, heat-treating the coated sample to decorate any agglomerated intrinsic point defects, cooling the sample, etching the surface of the cooled sample without delineating the decorated agglomerated intrinsic point defects and etching the etched surface with a delineating etchant to reveal the decorated intrinsic point defects.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: October 28, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Robert J. Falster
  • Publication number: 20030196587
    Abstract: The present invention relates to a process for growing a single crystal silicon ingot, which contains an axially symmetric region having a predominant intrinsic point defect and which is substantially free of agglomerated intrinsic point defects in that region. The process comprising cooling the ingot from the temperature of solidification to a temperature of less than 800° C. and, as part of said cooling step, quench cooling a region of the constant diameter portion of the ingot having a predominant intrinsic point defect through the temperature of nucleation for the agglomerated intrinsic point defects for the intrinsic point defects which predominate in the region.
    Type: Application
    Filed: May 6, 2003
    Publication date: October 23, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Kirk D. McCallum, W. Brock Alexander, Mohsen Banan, Robert J. Falster, Joseph C. Holzer, Bayard K. Johnson, Chang Bum Kim, Steven L. Kimbel, Zheng Lu, Paolo Mutti, Vladimir V. Voronkov, Luciano Mule'Stagno, Jeffrey L. Libbert
  • Patent number: 6635587
    Abstract: A process for heat treating a silicon wafer to dissolve B-type agglomerated interstitial defects present therein. The process includes heating the silicon wafer at a temperature for a time sufficient to dissolve B-defects, the wafer being heated to said temperature at a rate sufficient to prevent B-defects from becoming stabilized such that these defects are rendered incapable of being dissolved.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: October 21, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Jeffrey L. Libbert, Joseph C. Holzer
  • Publication number: 20030136961
    Abstract: A silicon wafer having a controlled oxygen precipitation behavior such that a denuded zone extending inward from the front surface and oxygen precipitates in the wafer bulk sufficient for intrinsic gettering purposes are ultimately formed. Specifically, prior to formation of the oxygen precipitates, the wafer bulk comprises dopant stabilized oxygen precipitate nucleation centers. The dopant is selected from a group consisting of nitrogen and carbon and the concentration of the dopant is sufficient to allow the oxygen precipitate nucleation centers to withstand thermal processing such as an epitaxial deposition process while maintaining the ability to dissolve any grown-in nucleation centers.
    Type: Application
    Filed: December 23, 2002
    Publication date: July 24, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Jeffrey L. Libbert, Richard J. Phillips, Milind Kulkarni, Mohsen Banan, Stephen J. Brunkhorst
  • Patent number: 6565649
    Abstract: The present invention is directed to an epitaxial wafer comprising a single crystal silicon substrate having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on the substrate surface upon which the epitaxial layer is deposited.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: May 20, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule′Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster
  • Publication number: 20020084451
    Abstract: The present invention is directed to an epitaxial silicon wafer, as well as to a process for the preparation thereof, wherein the substrate wafer is highly P-doped, has silicon lattice vacancies as the predominant intrinsic point defect and is substantially free of oxidation induced stacking faults and the epitaxial silicon layer grown on the substrate wafer is substantially free of grown in oxidation induced stacking faults.
    Type: Application
    Filed: November 7, 2001
    Publication date: July 4, 2002
    Inventors: Thomas C. Mohr, Luciano Mule' Stagno, Lu Fei, Mohsen Banan, Antonella Brianza
  • Patent number: 6391662
    Abstract: A process for revealing agglomerated intrinsic point defects in a single crystal silicon sample. The process includes heat-treating the single crystal silicon sample, cooling the heat-treated sample and then coating a surface of the cooled sample with a composition containing a metal which is capable of decorating agglomerated intrinsic point defects. The coated sample is then heat-treated in an inert atmosphere at a temperature and for a time sufficient to diffuse the metal into the sample. A non-defect delineating etch is performed, followed by a defect delineating etch to reveal the decorated agglomerated intrinsic point defects.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: May 21, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule′Stagno, Robert J. Falster
  • Publication number: 20020007779
    Abstract: The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects, and a process for the preparation thereof. The process for growing the single crystal silicon ingot comprises controlling (i) a growth velocity, v, (ii) an average axial temperature gradient, G0, during the growth of a constant diameter portion of the crystal over a temperature range from solidification to a temperature of no less than about 1325° C., and (iii) a cooling rate of the crystal from a solidification temperature to about 1,050° C., in order to cause the formation of an axially symmetrical segment which is substantially free of agglomerated intrinsic point defects.
    Type: Application
    Filed: December 30, 1999
    Publication date: January 24, 2002
    Inventors: LUCIANO MULE'STAGNO, ROBERT FALSTER
  • Publication number: 20010039916
    Abstract: The present invention is directed to a set of epitaxial silicon wafers assembled in a wafer cassette, boat or other wafer carrier. Each wafer comprises a single crystal silicon substrate having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on the substrate surface upon which the epitaxial layer is deposited.
    Type: Application
    Filed: June 5, 2001
    Publication date: November 15, 2001
    Inventors: Luciano Mule' Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Falster J. Falster
  • Patent number: 6284039
    Abstract: The present invention is directed to a set of epitaxial silicon wafers assembled in a wafer cassette, boat or other wafer carrier. Each wafer comprises a single crystal silicon substrate having an axially symmetric region in which silicon self-interstitials are the predominant intrinsic point defect and which is substantially free of agglomerated defects, and an epitaxial layer which is deposited upon a surface of the substrate and which is substantially free of grown-in defects caused by the presence of agglomerated silicon self-interstitial defects on the substrate surface upon which the epitaxial layer is deposited.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: September 4, 2001
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Luciano Mule'Stagno, Lu Fei, Joseph C. Holzer, Harold W. Korb, Robert J. Falster