Abstract: A semiconductor circuit according to an embodiment of the present disclosure includes a nonvolatile latch circuit that stores k-bit data, and m-bit error correction data for the k-bit data.

Abstract: A controller includes a processing circuit that writes each of a plurality of data fragments each including a part of data to be written in one memory chip of a plurality of memory chips each having an error correction function, and reads the data fragments corresponding to the data to be read from the memory chips, a first encoder that encodes the data to be written with an erasure correction code such that each of the data fragments includes a parity, and a first decoder that performs erasure correction by use of a part of the data fragments corresponding to the data to be read according to a completion status or success or failure of error correction on a corresponding part of the data fragments in each of the memory chips, the completion status or the success or failure of the error correction being acquired via a signal line.

Abstract: A memory cell array unit according to an embodiment of the present disclosure includes a memory cell array and a microcontroller. The memory cell array includes an n-bit allocation bit allocated from a memory controller in read/write control, and a redundant bit of one or a plurality of bits not being provided with a switching mechanism that switches as a substitution for a portion of the allocation bit. The microcontroller reads and writes n-bit data from and into the memory cell array using the allocation bit and the redundant bit on the basis of the read/write control from the memory controller.

Abstract: A memory cell array unit according to an embodiment of the present disclosure includes a microcontroller that performs reading and writing from and into a memory cell array using n-bit allocation memory cells on the basis of read/write control from a memory controller. When a defect is found in one of the n-bit allocation memory cells, the microcontroller writes n?1-bit write data excluding data of a least significant bit among n-bit write data into n?1-bit allocation memory cells excluding the defective allocation memory cell among the n-bit allocation memory cells.

Abstract: Provided are a controller and a storage device that achieve both high reliability and performance. A controller according to the present disclosure includes: a processing circuit configured to write each of a plurality of data fragments each including a part of data to be written in one memory chip of a plurality of memory chips each having an error correction function, and read the data fragments corresponding to the data to be read from the memory chips; a first encoder configured to encode the data to be written with an erasure correction code such that each of the data fragments includes a parity; and a first decoder configured to perform erasure correction by use of a part of the data fragments corresponding to the data to be read according to a completion status or success or failure of error correction on a corresponding part of the data fragments in each of the memory chips, the completion status or the success or failure of the error correction being acquired via a signal line.

Abstract: The present technology relates to a transmission device, a transmission method, a reception device, and a reception method that make it possible to more reliably transmit a transmission control signal. Provided is a transmission device including a transmission unit that includes a first transmission control signal compatible with a first system in a first broadcast signal including a signal of a first content compatible with the first system and a signal of a second content compatible with a second system and transmits the first broadcast signal via a first transmission antenna, and includes a second transmission control signal compatible with the second system in a second broadcast signal including the signal of the second content and transmits the second broadcast signal via a second transmission antenna. The present technology can be applied to, for example, a transmission system compatible with a broadcast system such as an ISDB-T system.

Abstract: The present technology relates to a transmission device, a transmission method, a reception device, and a reception method that make it possible to more reliably transmit a transmission control signal. Provided is a transmission device including a transmission unit that includes a first transmission control signal compatible with a first system in a first broadcast signal including a signal of a first content compatible with the first system and a signal of a second content compatible with a second system and transmits the first broadcast signal via a first transmission antenna, and includes a second transmission control signal compatible with the second system in a second broadcast signal including the signal of the second content and transmits the second broadcast signal via a second transmission antenna. The present technology can be applied to, for example, a transmission system compatible with a broadcast system such as an ISDB-T system.

Abstract: The present technology relates to a transmission device, a transmission method, a reception device, and a reception method that make it possible to improve transmission efficiency. Provided is a transmission device including a first time interleaver that performs first time interleaving conforming to a first system, on an error correction code block to be included as a data frame in a physical layer frame, in which the error correction code block conforms to a second system, and when performing the first time interleaving, the first time interleaver applies a pointer indicating an offset of a start position of the error correction code block included at a start of the data frame. The present technology can be applied to, for example, a transmission system compatible with a broadcast system such as an ISDB-T system.

Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data.

Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.

Abstract: To enable data to be transferred between a memory and a memory controller with accuracy. A memory-side interface circuit synchronizes a first periodic signal having a greater number of cycles than a number of pieces of unit data obtained by dividing read data read from a memory cell by a predetermined unit with the unit data and to sequentially transmit the first periodic signal and the unit data. A controller-side interface circuit sequentially holds the transmitted unit data in holding units of a plurality of stages in synchronization with the periodic signal and sequentially reads and outputs the held unit data in synchronization with a second periodic signal.

Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.

Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.

Abstract: Reduction in deterioration of a memory cell in a non-volatile memory is achieved. A memory controller is configured to include a time measuring unit, an elapsed time determination unit, and a read unit. The time measuring unit measures time elapsed from predetermined timing on an address where data written. The elapsed time determination unit determines whether the elapsed time exceeds a fixed amount of time upon receiving an instruction to read out the data from the address. The read control unit causes reading-out of the data from the address to pause in a case where the elapsed time is determined not to exceed the fixed amount of time.

Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.

Abstract: The convenience of an information processing system is improved. In a memory controller of the information processing system, a request generation unit generates, with respect to a nonvolatile memory including a data area in which data is stored and a redundancy area in which a redundancy for performing error detection and error correction of the data is stored, a request of requesting writing or reading for any one of the data, and the redundancy, a code word constituted of the data and the redundancy. A control unit issues the generated request and controls writing and reading with respect to the nonvolatile memory.

Abstract: A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data.

Abstract: An error detection-correction unit reads system information for operating a system from a first memory and performs error detection-correction processing. A control unit supplies the system information to a host computer in a case where the error detection-correction processing is successful. In addition, the control unit reads a backup of the system information from a second memory that is different from the first memory and supplies the backup of the system information to the host computer in a case where the detection-correction processing fails.

Abstract: A memory includes a buffer which retains data, a band conversion unit converts a band of an internal data bus that is used for data transfer between the band conversion unit and the buffer which retains data into a band wider than that of an external data bus that is used for data transfer between the band conversion unit and a memory controller, and an access control unit controls access to a memory cell using the buffer, during a wait time occurring in the internal data bus due to a difference between the band of the internal data bus and the band of the external data bus.

Abstract: Provided is a storage control device including: a detection unit which detects a first timing for performing a first rewriting process of performing only a first operation from among the first operation and a second operation, in a memory cell array in which each bit transitions to a first storage state by the first operation and transitions to a second storage state by the second operation; and a request unit which makes a request for the first rewriting process with respect to the memory cell array, when the first timing is detected.