Abstract: A hardware and/or software facility for controlling the order of operations performed by threads of a multithreaded application on a multiprocessing system is provided. The facility may serialize or selectively-serialize execution of the multithreaded application such that, given the same input to the multithreaded application, the multiprocessing system deterministically interleaves operations, thereby producing the same output each time the multithreaded application is executed. The facility divides the execution of the multithreaded application code into two or more quantum specifying a deterministic number of operations, and the facility specifies a deterministic order in which the threads execute the two or more quantum. The deterministic number of operations may be adapted to follow the critical path of the multithreaded application. Specified memory operations may be executed regardless of the deterministic order, such as those accessing provably local data.

Abstract: A computing system for scalable computing on commodity hardware is provided. The computing system includes a first computing device communicatively connected to a second computing device. The first computing device includes a processor, a physical computer-readable medium, and program instructions stored on the physical computer-readable medium and executable by the processor to perform functions. The functions include determining a first task associated with the second computing device and a second task associated with the second computing device are to be executed, assigning execution of the first task and the second task to the processor of the first computing device, generating an aggregated message that includes (i) a first message including an indication corresponding to the execution of the first task and (ii) a second message including an indication corresponding to the execution of the second task, and sending the aggregated message to the second computing device.

Abstract: Methods, servers, and systems for using signatures/certifications embedded in pre-processed code to enable use or reuse of pre-processed code to obviate the need to perform some operations or execute some scripts within the web page content. One or more operations may be performed within an executable script in web page content and signing the result of the operation in a manner that can be used to verify that the corresponding operation may be skipped by a browser. A browser receiving signed pre-processed code may use a signature verification process to determine whether the browser can bypass executing corresponding scripts in the web page content or perform alternative operations. Operations may be pre-performed and the results signed by off-line tools and included in the web page content. Results of operations may be stored in memory along with a signature so the results of the operation can be reused in the future.

Abstract: Devices and methods of providing hardware support for dynamic type checking are provided. In some embodiments, a processor includes a type check register and support for one or more checked load instructions. In some embodiments, normal load instructions are replaced by a compiler with the checked load instructions. In some embodiments, to perform a checked load, an error handler instruction location is stored in the type check register, and a type tag operand is compared to a type tag stored in the loaded memory location. If the comparison succeeds, execution may proceed normally. If the comparison fails, execution may be transferred to the error handler instruction. In some embodiments, type prediction is performed to determine whether a checked load instruction is likely to fail.

Abstract: A hardware and/or software facility for executing a multithreaded program is described. The facility causes each of a plurality of machines to execute the multithreaded program deterministically, such that the deterministic execution of the multithreaded program is replaced across the plurality of machines. The facility detects a problem in the execution of the multithreaded Program by one of the plurality of machines. In response, the facility adjusts the execution of the multithreaded program by at least one of the machines of the plurality.

Abstract: A system and method to trigger synchronization and validation actions at memory access, in one aspect, identifies a storage class associated with a region of shared memory being accessed by a thread, determines whether the thread holds the storage class and acquires the storage class if the thread does not hold the storage class, identifies a programmable action associated with the storage class and the thread, and triggers the programmable action. One or more storage classes are respectively associated with one or more regions of shared memory. An array of storage classes associated with a thread holds one or more storage classes acquired by the thread. A configurable action table associated with a thread indicates one or more programmable actions associated with a storage class.

Abstract: The aspects enable a computing device to execute traditionally software-based JavaScript® operations in hardware. Each JavaScript® object is hashed into a master hashtable that may be stored in the software. A portion of the software hashtable may be pushed to a hardware hashtable using special instruction set registers dedicated to hashtable processing. Each time a software process requests a hashtable operation (e.g., lookup) the hardware hashtable is checked to determine if the value exists in hardware. If the requested value is in the hardware hashtable, the requested value is accessed in a single operation step. If the requested value is not in the hardware hashtable, the requested value is extracted from the master hashtable in the software and a portion of the master hashtable containing the extracted value is pushed to the hardware using special instruction set registers.

Abstract: Systems and methods for detecting concurrency bugs are provided. In some embodiments, context-aware communication graphs that represent inter-thread communication are collected during test runs, and may be labeled according to whether the test run was correct or failed. Graph edges that are likely to be associated with failed behavior are determined, and probable reconstructions of failed behavior are constructed to assist in debugging. In some embodiments, software instrumentation is used to collect the communication graphs. In some embodiments, hardware configured to collect the communication graphs is provided.

Abstract: A hardware and/or software facility for executing a multithreaded program is described. The facility causes each of a plurality of machines to execute the multithreaded program deterministically, such that the deterministic execution of the multithreaded program is replaced across the plurality of machines. The facility detects a problem in the execution of the multithreaded Program by one of the plurality of machines. In response, the facility adjusts the execution of the multithreaded program by at least one of the machines of the plurality.

Abstract: Methods and devices for accelerating webpage rendering by a browser store document object model (DOM) tree structures and computations of rendered pages, and compare portions of a DOM tree of pages being render to determining if portions of the DOM tree structures match. If a DOM tree of a webpage to be rendered matches a DOM tree stored in memory, the computations associated with the match DOM tree may be recalled from memory, obviating the need to perform the calculations to render the page. A tree isomorphism algorithm may be used to recognize DOM trees stored in memory that match the DOM tree of the webpage to be rendered. Reusing rendering computations may significantly reducing the time and resources required for rendering web pages. Identifying reusable portions of calculation results based on DOM tree isomorphism enables the browser to reuse stored webpage rendering calculations even when URLs do not match.

Abstract: A hardware and/or software facility for controlling the order of operations performed by threads of a multithreaded application on a multiprocessing system is provided. The facility may serialize or selectively-serialize execution of the multithreaded application such that, given the same input to the multithreaded application, the multiprocessing system deterministically interleaves operations, thereby producing the same output each time the multithreaded application is executed. The facility divides the execution of the multithreaded application code into two or more quantum specifying a deterministic number of operations, and the facility specifies a deterministic order in which the threads execute the two or more quantum. The deterministic number of operations may be adapted to follow the critical path of the multithreaded application. Specified memory operations may be executed regardless of the deterministic order, such as those accessing provably local data.

Abstract: A system and method to trigger synchronization and validation actions at memory access, in one aspect, identifies a storage class associated with a region of shared memory being accessed by a thread, determines whether the thread holds the storage class and acquires the storage class if the thread does not hold the storage class, identifies a programmable action associated with the storage class and the thread, and triggers the programmable action. One or more storage classes are respectively associated with one or more regions of shared memory. An array of storage classes associated with a thread holds one or more storage classes acquired by the thread. A configurable action table associated with a thread indicates one or more programmable actions associated with a storage class.

Abstract: A method for handling permanent and transient errors in a microprocessor is disclosed. The method includes reading a scalar value and a scalar operation from an execution unit of the microprocessor. The method further includes writing a copy of the scalar value into each of a plurality of elements of a vector register of a Single Instruction Multiple Data (SIMD) unit of the microprocessor and executing the scalar operation on each scalar value in each of the plurality of elements of the vector register of the SIMED unit using a vector operation. The method further includes comparing each result of the scalar operation on each scalar value in each of the plurality of elements of the vector register and detecting a permanent or transient error if all of the results are not identical.